Datasheet LT8709 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Negative Input Synchronous Multi-Topology DC/DC Controller |
| Pages / Page | 48 / 10 — PIN FUNCTIONS. CSN, CSP (Pins 14, 15):. MODE (Pin 17):. EN/FBIN (Pin … |
| File Format / Size | PDF / 802 Kb |
| Document Language | English |
PIN FUNCTIONS. CSN, CSP (Pins 14, 15):. MODE (Pin 17):. EN/FBIN (Pin 16):. RT (Pin 18):. SYNC (Pin 19):
Model Line for this Datasheet
Text Version of Document
LT8709
PIN FUNCTIONS CSN, CSP (Pins 14, 15):
NFET Current Sense Negative
MODE (Pin 17):
DCM/CCM Mode Pin. Its voltage is referred and Positive Input Pins Respectively. Kelvin connect to the –VIN pin. Drive the pin below 1.175V (typical) to these pins to a sense resistor to control the NFET switch operate in forced CCM. Drive the pin above 1.224V (typi- current. The maximum sense voltage at low duty cycle is cal) to operate in DCM and/or pulse-skipping mode at light 50mV (typical). loads. If SS < 1.8V (typical) or INTVEE is in UVLO, the part
EN/FBIN (Pin 16):
Enable and Input Voltage Regulation will operate in DCM at light load. Pin. Its voltage is referred to the –VIN pin. In conjunction
RT (Pin 18):
Timing Resistor Pin. Adjusts the LT8709’s with the INTVCC and INTVEE UVLO (undervoltage lockout) switching frequency. Place a resistor from this pin to –VIN circuits, overtemperature protection and output overcur- to set the frequency to a fixed free running level. Do not rent protection; this pin is used to enable/disable the chip float this pin. and restart the soft-start sequence. The EN/FBIN pin is
SYNC (Pin 19):
External Clock Input Pin. Its voltage is also used to limit the NFET current to avoid collapsing referred to the –V the input supply. Drive the pin below 0.3V to disable the IN pin. To synchronize the switching frequency to an outside clock, simply drive this pin with a chip with very low quiescent current. Drive the pin above clock to override the internal clock. The logic-high voltage 1.7V (typical) to activate the chip and restart the soft-start level of the SYNC clock must exceed 1.5V, and the logic- sequence. The commanded NFET current will be controlled low level must be less than 0.4V. Drive this pin to less by the EN/FBIN amplifier when the voltage drops between than 0.4V to revert to the internal free running clock. See 1.55V and 1.662V. See the Block Diagram and Applica- the Applications Information section for more information. tions section for more information. Do not float this pin.
–VIN (Pin 20, Exposed Pad Pin 21):
Negative Voltage Input Pin. Since –VIN also serves as the chip ground, it must be soldered onto a local –VIN plane on the PCB. 8709fa 10 For more information www.linear.com/LT8709
PIN FUNCTIONS CSN, CSP (Pins 14, 15):
NFET Current Sense Negative
MODE (Pin 17):
DCM/CCM Mode Pin. Its voltage is referred and Positive Input Pins Respectively. Kelvin connect to the –VIN pin. Drive the pin below 1.175V (typical) to these pins to a sense resistor to control the NFET switch operate in forced CCM. Drive the pin above 1.224V (typi- current. The maximum sense voltage at low duty cycle is cal) to operate in DCM and/or pulse-skipping mode at light 50mV (typical). loads. If SS < 1.8V (typical) or INTVEE is in UVLO, the part
EN/FBIN (Pin 16):
Enable and Input Voltage Regulation will operate in DCM at light load. Pin. Its voltage is referred to the –VIN pin. In conjunction
RT (Pin 18):
Timing Resistor Pin. Adjusts the LT8709’s with the INTVCC and INTVEE UVLO (undervoltage lockout) switching frequency. Place a resistor from this pin to –VIN circuits, overtemperature protection and output overcur- to set the frequency to a fixed free running level. Do not rent protection; this pin is used to enable/disable the chip float this pin. and restart the soft-start sequence. The EN/FBIN pin is
SYNC (Pin 19):
External Clock Input Pin. Its voltage is also used to limit the NFET current to avoid collapsing referred to the –V the input supply. Drive the pin below 0.3V to disable the IN pin. To synchronize the switching frequency to an outside clock, simply drive this pin with a chip with very low quiescent current. Drive the pin above clock to override the internal clock. The logic-high voltage 1.7V (typical) to activate the chip and restart the soft-start level of the SYNC clock must exceed 1.5V, and the logic- sequence. The commanded NFET current will be controlled low level must be less than 0.4V. Drive this pin to less by the EN/FBIN amplifier when the voltage drops between than 0.4V to revert to the internal free running clock. See 1.55V and 1.662V. See the Block Diagram and Applica- the Applications Information section for more information. tions section for more information. Do not float this pin.
–VIN (Pin 20, Exposed Pad Pin 21):
Negative Voltage Input Pin. Since –VIN also serves as the chip ground, it must be soldered onto a local –VIN plane on the PCB. 8709fa 10 For more information www.linear.com/LT8709
