Datasheet LTC1771 (Analog Devices) - 9

ManufacturerAnalog Devices
Description10µA Quiescent Current High Efficiency Step-Down DC/DC Controller
Pages / Page16 / 9 — APPLICATIO S I FOR ATIO. Efficiency Considerations
File Format / SizePDF / 243 Kb
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APPLICATIO S I FOR ATIO. Efficiency Considerations

APPLICATIO S I FOR ATIO Efficiency Considerations

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LTC1771
U U W U APPLICATIO S I FOR ATIO
ripple current ratings are often based on 2000 hours of life. size of any aluminum electrolytic at a somewhat higher This makes it advisable to further derate the capacitor, or price. Typically once the ESR requirement is satisfied, the to choose a capacitor rated at a higher temperature than RMS current rating generally far exceeds the IRIPPLE(P-P) required. Do not underspecify this component. An addi- requirement. tional 0.1µF ceramic capacitor is also helpful on VIN for In surface mount applications multiple capacitors may high frequency decoupling. have to be paralleled to meet the ESR or RMS current The selection of COUT is driven by the required effective handling requirements of the application. Aluminum series resistance (ESR). Typically, once the ESR require- electrolytics and dry tantalum capacitors are both available ment is satisfied, the capacitance is adequate for filtering. in surface mount configurations. In case of tantalum, it is The output ripple (∆VOUT) in continuous mode is approxi- critical that the capacitors are surge tested for use in mated by: switching power supplies. An excellent choice is the  AVX TPS, AVX TPSV and KEMET T510 series of surface 1  ∆V mount tantalums, available in case heights ranging from OUT ≈ I ESR RIPPLE +  8fCOUT  2mm to 4mm. Other capacitor types include Sanyo OS-CON, Sanyo POSCAP, Nichicon PL series and where f is the operating frequency, COUT is the output Panasonic SP. capacitance and IRIPPLE is the ripple current in the inductor. For output ripple less than 100mV, assure COUT
Efficiency Considerations
required ESR is <2RSENSE. The efficiency of a switching regulator is equal to the The first condition relates to the ripple current into the ESR output power divided by the input power times 100%. It is of the output capacitance while the second term guaran- often useful to analyze individual losses to determine what tees that the output capacitance does not significantly is limiting efficiency and which change would produce the discharge during the operating frequency period due to most improvement. Efficiency can be expressed as: ripple current. The choice of using smaller output capaci- tance increases the ripple voltage due to the discharging Efficiency = 100% – (L1 + L2 +L3 + ...) term but can be compensated for by using capacitors of where L1, L2, etc. are the individual losses as a percentage very low ESR to maintain the ripple voltage at or below of input power. 50mV. The ITH pin OPTI-LOOPTM compensation compo- Although all dissipative elements in the circuit produce nents can be optimized to provide stable, high perfor- losses, four main sources usually account for most of the mance transient response regardless of the output losses in the LTC1771 circuits: the LTC1771 DC bias capacitors selected. current, MOSFET gate charge current, I2R losses and When running into dropout, extra input and output capaci- catch diode losses. tance may be necessary for optimal performance due to 1. The DC bias current is 9µA at no load and increases the drop in frequency as the duty cycle approaches 100%. proportionally with load up to a constant 150µA during Compare Figure 1 to the low dropout regulators shown in continuous mode. This bias current is so small that this the Typical Applications section for recommended CIN, loss is negligible at loads above a milliamp but at no COUT, CFF and CC values for low dropout regulators vs load accounts for nearly all of the loss. regulators not requiring low dropout. 2. The MOSFET gate charge current results from switch- Manufacturers such as Nichicon, United Chemicon and ing the gate capacitance of the power MOSFET switch. Sanyo should be considered for high performance through- Each time the gate is switched from high to low to high hole capacitors. The OS-CON semiconductor dielectric again, a packet of charge dQ moves from V capacitor available from Sanyo has the lowest ESR for its IN to ground. The resulting dQ/dt is the current out of VIN which is OPTI-LOOP is a trademark of Linear Technology Corporation. typically much larger than the DC bias current. In 9