Datasheet LTC3423, LTC3424 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Low Output Voltage, 3MHz Micropower Synchronous Boost Converters |
| Pages / Page | 12 / 10 — APPLICATIO S I FOR ATIO. Figure 3. TYPICAL APPLICATIO. Typical … |
| File Format / Size | PDF / 211 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Figure 3. TYPICAL APPLICATIO. Typical Application with Output Disconnect
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Text Version of Document
LTC3423/LTC3424
U U W U APPLICATIO S I FOR ATIO
GDC = GCONTROLOUTPUT • GEA The typical error amp compensation is shown in Figure 3. The equations for the loop dynamics are as follows: V G IN CONTROL = 2 • , G I EA ≈ 2000 OUT 1 f ≈ Hz POLE1 The output filter pole is given by: 6 2 • π • 20 •10 • CC1 which is extremelyclose to DC I f OUT = Hz FILTERPOLE π 1 • V • C = OUT OUT f Hz ZERO1 2 • π •R • C Z C1 where COUT is the output filter capacitor. 1 ≈ The output filter zero is given by: f Hz POLE2 2 • π •R • C Z C2 f = 1 Hz FILTERZERO 2 • π • R • C Refer to Application Note AN76 for more closed loop ESR OUT examples. where RESR is the capacitor equivalent series resistance. A troublesome feature of the boost regulator topology is VOUT the right half plane zero (RHP) and is given by: + 1.25V ERROR R1 FB AMP 2 – 8 V •R f IN O = Hz RHPZ V R2 C 2 2 • π • L • V 9 O CC1 CC2 At heavy loads this gain increase with phase lag can occur RZ at a relatively low frequency. The loop gain is typically 3423/24 F03 rolled off before the RHP zero frequency.
Figure 3 U TYPICAL APPLICATIO Typical Application with Output Disconnect
ZETEX VIN = 0.9V TO 1.5V FMMT717 VOUT LTC3423/LTC3424 3 4 VIN SW RB* 10 7 SHDN VOUT 2 8 C5 MODE/SYNC FB 1µF 6 9 VDD VDD VC 1 5 Rt GND 3423/24 TA03 (V * SET RB TO FORCE BETA OF ≤100; RB = OUT – VINMIN – 0.7V) • 100 IOUTMAX 0 = FIXED FREQ 1 = Burst Mode OPERATION 34234f 10
U U W U APPLICATIO S I FOR ATIO
GDC = GCONTROLOUTPUT • GEA The typical error amp compensation is shown in Figure 3. The equations for the loop dynamics are as follows: V G IN CONTROL = 2 • , G I EA ≈ 2000 OUT 1 f ≈ Hz POLE1 The output filter pole is given by: 6 2 • π • 20 •10 • CC1 which is extremelyclose to DC I f OUT = Hz FILTERPOLE π 1 • V • C = OUT OUT f Hz ZERO1 2 • π •R • C Z C1 where COUT is the output filter capacitor. 1 ≈ The output filter zero is given by: f Hz POLE2 2 • π •R • C Z C2 f = 1 Hz FILTERZERO 2 • π • R • C Refer to Application Note AN76 for more closed loop ESR OUT examples. where RESR is the capacitor equivalent series resistance. A troublesome feature of the boost regulator topology is VOUT the right half plane zero (RHP) and is given by: + 1.25V ERROR R1 FB AMP 2 – 8 V •R f IN O = Hz RHPZ V R2 C 2 2 • π • L • V 9 O CC1 CC2 At heavy loads this gain increase with phase lag can occur RZ at a relatively low frequency. The loop gain is typically 3423/24 F03 rolled off before the RHP zero frequency.
Figure 3 U TYPICAL APPLICATIO Typical Application with Output Disconnect
ZETEX VIN = 0.9V TO 1.5V FMMT717 VOUT LTC3423/LTC3424 3 4 VIN SW RB* 10 7 SHDN VOUT 2 8 C5 MODE/SYNC FB 1µF 6 9 VDD VDD VC 1 5 Rt GND 3423/24 TA03 (V * SET RB TO FORCE BETA OF ≤100; RB = OUT – VINMIN – 0.7V) • 100 IOUTMAX 0 = FIXED FREQ 1 = Burst Mode OPERATION 34234f 10
