Datasheet LTC3704 (Analog Devices) - 9

LTC3704
U OPERATIO
minimum on-time (about 175ns). Below this output buffered ITH burst clamp is removed, allowing the ITH pin current level, the converter will begin to skip cycles in to directly control the current comparator from no load to order to maintain output regulation. Figures 3 and 4 show full load. With no load, the ITH pin is driven below 0.30V, the light load switching waveforms for Burst Mode and the power MOSFET is turned off and sleep mode is Pulse-Skip Mode operation for the converter in Figure 1. invoked. Oscilloscope waveforms illustrating this mode of operation are shown in Figure 4.
Burst Mode Operation
MODE/SYNC = INTV Burst Mode operation is selected by leaving the MODE/ CC (PULSE-SKIP MODE) SYNC pin unconnected or by connecting it to ground. In normal operation, the range on the I VOUT TH pin corresponding 50mV/DIV to no load to full load is 0.30V to 1.2V. In Burst Mode operation, if the error amplifier EA drives the ITH voltage below 0.525V, the buffered ITH input to the current com- parator C1 will be clamped at 0.525V (which corresponds IL to 25% of maximum load current). The inductor current 5A/DIV peak is then held at approximately 30mV divided by the 2μs/DIV 3704 F04 power MOSFET RDS(ON). If the ITH pin drops below 0.30V, the Burst Mode comparator B1 will turn off the power
Figure 4. LTC3704 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTV
MOSFET and scale back the quiescent current of the IC to
CC)
250μA (sleep mode). In this condition, the load current will be supplied by the output capacitor until the I When an external clock signal drives the MODE/SYNC pin TH voltage rises above the 50mV hysteresis of the burst comparator. at a rate faster than the chip’s internal oscillator, the At light loads, short bursts of switching (where the aver- oscillator will synchronize to it. In this synchronized mode, age inductor current is 25% of its maximum value) fol- Burst Mode operation is disabled. The constant frequency lowed by long periods of sleep will be observed, thereby associated with synchronized operation provides a more greatly improving converter efficiency. Oscilloscope wave- controlled noise spectrum from the converter, at the forms illustrating Burst Mode operation are shown in expense of overall system efficiency of light loads. Figure 3. When the oscillator’s internal logic circuitry detects a synchronizing signal on the MODE/SYNC pin, the internal MODE/SYNC = 0V oscillator ramp is terminated early and the slope compen- (Burst Mode OPERATION) sation is increased by approximately 30%. As a result, in VOUT 50mV/DIV applications requiring synchronization, it is recommended that the nominal operating frequency of the IC be pro- grammed to be about 75% of the external clock frequency. Attempting to synchronize to too high an external fre- IL 5A/DIV quency (above 1.3fO) can result in inadequate slope com- pensation and possible subharmonic oscillation (or jitter). 10μs/DIV 3704 F03 The external clock signal must exceed 2V for at least 25ns, and should have a maximum duty cycle of 80%, as shown
Figure 3. LTC3704 Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current
in Figure 5. The MOSFET turn on will synchronize to the rising edge of the external clock signal.
Pulse-Skip Mode Operation
With the MODE/SYNC pin tied to a DC voltage above 1.2V, Burst Mode operation is disabled. The internal, 0.525V 3704fb 9