Datasheet LTC3713 (Analog Devices) - 10

LTC3713
U OPERATIO
switch cycle, turning on the switch. When the summation response can be optimized by the addition of a phase lead of a signal representing switch current and a ramp gen- capacitor CPL in parallel with R7 in applications where erator (introduced to avoid subharmonic oscillations at large value or low ESR output capacitors are used. duty factors greater than 50%) exceeds the VC signal, As the load current is decreased, the switch turns on for comparator A2 changes state, resetting the flip-flop and a shorter period each cycle. If the load current is further turning off the switch. More power is delivered to the decreased, the boost converter will skip cycles to main- output as switch current is increased. The output voltage, tain output voltage regulation. If the V attenuated by external resistor divider R7 and R8, appears FB2 pin voltage is increased significantly above 1.23V, the boost converter at the VFB2 pin, closing the overall loop. Frequency com- will enter a low power state. pensation is provided internally by RC and CC. Transient
U U W U APPLICATIO S I FOR ATIO
A typical LTC3713 application circuit is shown in resulting in nominal sense voltages of 50mV to 200mV. Figure 1. External component selection is primarily de- Additionally, the VRNG pin can be tied to SGND or INTVCC termined by the maximum load current and begins with in which case the nominal sense voltage defaults to 70mV the selection of the sense resistance and power MOSFET or 140mV, respectively. The maximum allowed sense switches. The LTC3713 uses the on-resistance of the voltage is about 1.33 times this nominal value. synchronous power MOSFET for determining the induc- tor current. The desired amount of ripple current and
Connecting the SENSE+ and SENSE– Pins
operating frequency largely determines the inductor value. The LTC3713 can be used with or without a sense resistor. Finally, CIN is selected for its ability to handle the large When using a sense resistor, it is placed between the RMS current into the converter and COUT is chosen with source of the bottom MOSFET M2 and ground. Connect low enough ESR to meet the output voltage ripple and the SENSE+ and SENSE– pins as a Kelvin connection to the transient specification. sense resistor with SENSE+ at the source of the bottom
Maximum Sense Voltage and V
MOSFET and the SENSE – pin to PGND1. Using a sense
RNG Pin
resistor provides a well defined current limit, but adds cost Inductor current is determined by measuring the voltage and reduces efficiency. Alternatively, one can eliminate the across a sense resistance that appears between the sense resistor and use the bottom MOSFET as the current SENSE+ and SENSE– pins. The maximum sense voltage sense element by simply connecting the SENSE+ pin to the is set by the voltage applied to the VRNG pin and is equal drain and the SENSE– pin to the source of the bottom to approximately (0.133)VRNG. The current mode control MOSFET. This improves efficiency, but one must carefully loop will not allow the inductor current valleys to exceed choose the MOSFET on-resistance as discussed in a later (0.133)VRNG/RSENSE. In practice, one should allow some section. margin for variations in the LTC3713 and external com- ponent values and a good guide for selecting the sense
Applications Requiring Symmetric Current Limit
resistance is: The ITH voltage has a range of 0V to 2.4V with 0.8V V corresponding to 0A. In applications in which the output R RNG SENSE = 10•I will only be sourcing current, this allows the output to sink OUT MAX ( ) one third of the maximum source current. For applications An external resistive divider from INTVCC can be used to in which the output will be sourcing and sinking current, set the voltage of the VRNG pin between 0.5V and 2V it might be desirable to have a symmetrical output current 3713fa 10