Datasheet ADAQ7980, ADAQ7988 (Analog Devices) - 7

Data Sheet ADAQ7980/ADAQ7988 SINGLE-SUPPLY CONFIGURATION
VDD = V+ = 5.0 V, V− = 0 V, VIO = 1.7 V to 5.5 V, VREF = 3.3 V, TA = −55°C to +125°C, the ADC driver in a unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted.
Table 4. Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits SYSTEM ACCURACY Differential Nonlinearity Error1 −14 ±7 +14 ppm2 Integral Nonlinearity Error1 −20 ±8 +20 ppm2 Transition Noise 0.8 LSB2 rms Gain Error TA = 25°C −0.013 ±0.002 +0.013 %FS Gain Error Temperature Drift 0.1 0.4 ppm/°C Zero Error TA = 25°C −0.5 ±0.06 +0.5 mV Zero Error Temperature Drift 0.35 1.75 µV/°C Common-Mode Rejection Ratio 103 133 dB Power Supply Rejection Ratio Positive V+ = 4.5 V to 5.5 V, V− = 0 V 75 92 dB SYSTEM AC PERFORMANCE Dynamic Range 89 dB3 Total RMS Noise 41.4 µV rms Oversampled Dynamic Range fODR = 10 kSPS 109 dB3 Signal-to-Noise Ratio Input frequency (fIN) = 10 kHz 87.3 88.7 dB3 Spurious-Free Dynamic Range fIN = 10 kHz 103 dB3 Total Harmonic Distortion fIN = 10 kHz −113 −100 dB3 Signal-to-Noise-and-Distortion Ratio fIN = 10 kHz 87 88.4 dB3 Effective Number of Bits fIN = 10 kHz 14.1 14.4 Bits Noise Free Code Resolution 13.5 Bits SYSTEM SAMPLING DYNAMICS Conversion Rate ADAQ7980 VIO ≥ 3.0 V 0 1 MSPS VIO ≥ 1.7 V 0 833 kSPS ADAQ7988 VIO ≥ 1.7 V 0 500 kSPS Transient Response Full-scale step 430 500 ns −3 dB Input Bandwidth ADC driver RC filter 4.42 MHz −1 dB Frequency ADC driver RC filter 2.2 MHz −0.1 dB Frequency ADC driver RC filter 0.67 MHz 0.1 Hz to 10 Hz Voltage Noise 17 µV p-p Aperture Delay 2.0 ns Aperture Jitter 2.0 ns 1 Nonlinearity guaranteed over input voltage range. Codes below 150 mV are not represented with a unipolar supply configuration. 2 LSB means least significant bit. With the 3.3 V input range, 1 LSB = 50.4 µV, and 1 LSB = 15.26 ppm. 3 All specifications in dB are referred to a full-scale input, FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. A | Page 7 of 49 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL-SUPPLY CONFIGURATION SINGLE-SUPPLY CONFIGURATION TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ADC DRIVER INPUT INPUT PROTECTION NOISE CONSIDERATIONS AND SIGNAL SETTLING OPERATION DYNAMIC POWER SCALING (DPS) SLEW ENHANCEMENT EFFECT OF FEEDBACK RESISTOR ON FREQUENCY RESPONSE VOLTAGE REFERENCE INPUT POWER SUPPLY LDO REGULATOR CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION LDO REGULATOR THERMAL CONSIDERATIONS DIGITAL INTERFACE 3-WIRE MODE WITHOUT THE BUSY INDICATOR 3-WIRE MODE WITH THE BUSY INDICATOR 4-WIRE MODE WITHOUT THE BUSY INDICATOR 4-WIRE MODE WITH THE BUSY INDICATOR CHAIN MODE WITHOUT THE BUSY INDICATOR CHAIN MODE WITH THE BUSY INDICATOR APPLICATION CIRCUITS NONUNITY GAIN CONFIGURATIONS INVERTING CONFIGURATION WITH LEVEL SHIFT USING THE ADAQ7980/ADAQ7988 WITH ACTIVE FILTERS APPLICATIONS INFORMATION LAYOUT EVALUATING THE PERFORMANCE OF THE ADAQ7980/ADAQ7988 OUTLINE DIMENSIONS ORDERING GUIDE