Datasheet AD7779 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 8-Channel, 24-Bit, Simultaneous Sampling ADC |
| Pages / Page | 101 / 3 — AD7779. Data Sheet. TABLE OF CONTENTS |
| Revision | C |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
AD7779. Data Sheet. TABLE OF CONTENTS
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AD7779 Data Sheet TABLE OF CONTENTS
Features .. 1 Σ-∆ Output Data ... 51 Applications ... 1 ADC Conversion Output—Header and Data .. 51 General Description ... 1 Sample Rate Converter (SRC) (SPI COntrol MOde) .. 52 Revision History ... 4 Data Output Interface .. 54 Functional Block Diagram .. 5 Calculating the CRC Checksum .. 58 Specifications ... 6 Register Summary .. 60 DOUTx Timing Characterististics ... 10 Register Details ... 64 SPI Timing Characterististics ... 11 Channel 0 Configuration Register ... 64 Synchronization Pins and Reset Timing Characteristics .. 12 Channel 1 Configuration Register ... 64 SAR ADC Timing Characterististics ... 13 Channel 2 Configuration Register ... 65 GPIO SRC Update Timing Characterististics... 13 Channel 3 Configuration Register ... 65 Absolute Maximum Ratings .. 14 Channel 4 Configuration Register ... 66 Thermal Resistance .. 14 Channel 5 Configuration Register ... 66 ESD Caution .. 14 Channel 6 Configuration Register ... 67 Pin Configuration and Function Descriptions ... 15 Channel 7 Configuration Register ... 67 Typical Performance Characteristics ... 18 Disable Clocks to ADC Channel Register .. 68 Terminology .. 31 Channel 0 Sync Offset Register .. 68 RMS Noise and Resolution.. 33 Channel 1 Sync Offset Register .. 68 High Resolution Mode ... 33 Channel 2 Sync Offset Register .. 69 Low Power Mode .. 33 Channel 3 Sync Offset Register .. 69 Theory of Operation .. 34 Channel 4 Sync Offset Register .. 69 Analog Inputs .. 34 Channel 5 Sync Offset Register .. 69 Transfer Function ... 35 Channel 6 Sync Offset Register .. 70 Core Signal Chain... 36 Channel 7 Sync Offset Register .. 70 Capacitive PGA ... 36 General User Configuration 1 Register ... 70 Internal Reference and Reference Buffers ... 36 General User Configuration 2 Register ... 71 Integrated LDOs ... 37 General User Configuration 3 Register ... 72 Clocking and Sampling .. 37 Data Output Format Register ... 72 Digital Reset and Synchronization Pins .. 37 Main ADC Meter and Reference Mux Control Register .. 73 Digital Filtering ... 38 Global Diagnostics Mux Register ... 74 Shutdown Mode .. 38 GPIO Configuration Register ... 75 Control ing the AD7779 .. 39 GPIO Data Register.. 75 Pin Control Mode ... 39 Buffer Configuration 1 Register ... 75 SPI Control .. 41 Buffer Configuration 2 Register ... 76 Digital SPI Interface ... 44 Channel 0 Offset Upper Byte Register... 76 Diagnostics and Monitoring ... 47 Channel 0 Offset Middle Byte Register ... 76 Self Diagnostics Error .. 47 Channel 0 Offset Lower Byte Register ... 77 Monitoring Using the AD7779 SAR ADC (SPI Control Channel 0 Gain Upper Byte Register ... 77 Mode) ... 48 Channel 0 Gain Middle Byte Register ... 77 Σ-Δ ADC Diagnostics (SPI Control Mode) .. 50 Channel 0 Gain Lower Byte Register ... 77 Rev. B | Page 2 of 100 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7779 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIO Pins Σ-∆ Reference Configuration Power Modes LDO Bypassing DIGITAL SPI INTERFACE SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-∆ Data, ADC Mode SPI Software Reset DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and MEMMAP CRC Σ-∆ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7779 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header ERROR Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay and Latency Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI Interface CALCULATING THE CRC CHECKSUM Σ-∆ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
AD7779 Data Sheet TABLE OF CONTENTS
Features .. 1 Σ-∆ Output Data ... 51 Applications ... 1 ADC Conversion Output—Header and Data .. 51 General Description ... 1 Sample Rate Converter (SRC) (SPI COntrol MOde) .. 52 Revision History ... 4 Data Output Interface .. 54 Functional Block Diagram .. 5 Calculating the CRC Checksum .. 58 Specifications ... 6 Register Summary .. 60 DOUTx Timing Characterististics ... 10 Register Details ... 64 SPI Timing Characterististics ... 11 Channel 0 Configuration Register ... 64 Synchronization Pins and Reset Timing Characteristics .. 12 Channel 1 Configuration Register ... 64 SAR ADC Timing Characterististics ... 13 Channel 2 Configuration Register ... 65 GPIO SRC Update Timing Characterististics... 13 Channel 3 Configuration Register ... 65 Absolute Maximum Ratings .. 14 Channel 4 Configuration Register ... 66 Thermal Resistance .. 14 Channel 5 Configuration Register ... 66 ESD Caution .. 14 Channel 6 Configuration Register ... 67 Pin Configuration and Function Descriptions ... 15 Channel 7 Configuration Register ... 67 Typical Performance Characteristics ... 18 Disable Clocks to ADC Channel Register .. 68 Terminology .. 31 Channel 0 Sync Offset Register .. 68 RMS Noise and Resolution.. 33 Channel 1 Sync Offset Register .. 68 High Resolution Mode ... 33 Channel 2 Sync Offset Register .. 69 Low Power Mode .. 33 Channel 3 Sync Offset Register .. 69 Theory of Operation .. 34 Channel 4 Sync Offset Register .. 69 Analog Inputs .. 34 Channel 5 Sync Offset Register .. 69 Transfer Function ... 35 Channel 6 Sync Offset Register .. 70 Core Signal Chain... 36 Channel 7 Sync Offset Register .. 70 Capacitive PGA ... 36 General User Configuration 1 Register ... 70 Internal Reference and Reference Buffers ... 36 General User Configuration 2 Register ... 71 Integrated LDOs ... 37 General User Configuration 3 Register ... 72 Clocking and Sampling .. 37 Data Output Format Register ... 72 Digital Reset and Synchronization Pins .. 37 Main ADC Meter and Reference Mux Control Register .. 73 Digital Filtering ... 38 Global Diagnostics Mux Register ... 74 Shutdown Mode .. 38 GPIO Configuration Register ... 75 Control ing the AD7779 .. 39 GPIO Data Register.. 75 Pin Control Mode ... 39 Buffer Configuration 1 Register ... 75 SPI Control .. 41 Buffer Configuration 2 Register ... 76 Digital SPI Interface ... 44 Channel 0 Offset Upper Byte Register... 76 Diagnostics and Monitoring ... 47 Channel 0 Offset Middle Byte Register ... 76 Self Diagnostics Error .. 47 Channel 0 Offset Lower Byte Register ... 77 Monitoring Using the AD7779 SAR ADC (SPI Control Channel 0 Gain Upper Byte Register ... 77 Mode) ... 48 Channel 0 Gain Middle Byte Register ... 77 Σ-Δ ADC Diagnostics (SPI Control Mode) .. 50 Channel 0 Gain Lower Byte Register ... 77 Rev. B | Page 2 of 100 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7779 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIO Pins Σ-∆ Reference Configuration Power Modes LDO Bypassing DIGITAL SPI INTERFACE SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-∆ Data, ADC Mode SPI Software Reset DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and MEMMAP CRC Σ-∆ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7779 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header ERROR Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay and Latency Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI Interface CALCULATING THE CRC CHECKSUM Σ-∆ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
