Datasheet AD7770 (Analog Devices)

8-Channel, 24-Bit, Simultaneous Sampling ADC Data Sheet AD7770 FEATURES
The analog inputs accept unipolar (0 V to VREF) or true bipolar
8-channel, 24-bit simultaneous sampling analog-to-digital
(±VREF/2) analog input signals with 3.3 V or ±1.65 V analog
converter (ADC)
supply voltages, respectively for PGAGAIN = 1. The analog inputs
Single-ended or true differential inputs
can be configured to accept true differential, pseudo differential,
Programmable gain amplifier (PGA) per channel (gains of
or single-ended signals to match different sensor output
1, 2, 4, and 8)
configurations.
Low dc input current
Each channel contains a PGA, an ADC modulator and a
±4 nA (differential) and ±8 nA (single-ended)
sinc3, low latency digital filter. An SRC is provided to allow fine
Up to 32 kSPS output data rate (ODR) per channel
resolution control over the AD7770 ODR. This control can be
Programmable ODRs and bandwidth
used in applications where the ODR resolution is required to
Sample rate converter (SRC) for coherent sampling
maintain coherency with 0.01 Hz changes in the line frequency.
Sampling rate resolution up to 15.2 × 10−6 SPS
The SRC is programmable through the serial port interface (SPI).
Low latency sinc3 filter path
The AD7770 implements two different interfaces: a data output
Adjustable phase synchronization
interface and SPI control interface. The ADC data output interface
Internal 2.5 V reference
is dedicated to transmitting the ADC conversion results from
Two power modes optimizing power dissipation and
the AD7770 to the processor. The SPI writes to and reads from
performance: high resolution mode and low power mode
the AD7770 configuration registers and for the control and
Low resolution successive approximation register (SAR) ADC
reading of data from the SAR ADC. The SPI can also be
for system and chip diagnostics
configured to output the Σ-Δ conversion data.
Power supply
The AD7770 includes a 12-bit SAR ADC. This ADC can be
Bipolar (±1.65 V) or unipolar (3.3 V) supplies
used for AD7770 diagnostics without having to decommission
Digital input/output (I/O) supply: 1.8 V to 3.6 V
one of the Σ-Δ ADC channels dedicated to system measurement
Performance temperature range: −40°C to +105°C
functions. With the use of an external multiplexer, which can be
Functional temperature range: −40°C to +125°C Performance
controlled through the three general-purpose input/output pins
Combined ac and dc performance
(GPIOs), and signal conditioning, the SAR ADC can validate
103 dB dynamic range at 32 kSPS in high resolution mode
the Σ-Δ ADC measurements in applications where functional
−109 dB total harmonic distortion (THD)
safety is required. In addition, the AD7770 SAR ADC includes
±9 ppm of FSR integral nonlinearity (INL)
an internal multiplexer to sense internal nodes.
±15 µV offset error
The AD7770 contains a 2.5 V reference and reference buffer. The
±0.1% FS gain error
reference has a typical temperature coefficient of 10 ppm/°C.
±10 ppm/°C typical temperature coefficient
The AD7770 offers two modes of operation: high resolution mode
APPLICATIONS
and low power mode. High resolution mode provides a higher dynamic range while consuming 10.75 mW per channel; low
Protection relays
power mode consumes just 3.37 mW per channel at a reduced
General-purpose data acquisition
dynamic range specification.
Industrial process control
The specified operating temperature range is −40°C to +105°C,
GENERAL DESCRIPTION
although the device is operational up to +125°C. The AD7770 is an 8-channel, simultaneous sampling ADC. Eight Note that throughout this data sheet, certain terms are used to full sigma-delta (Σ-Δ) ADCs are on chip. The AD7770 provides refer to either the multifunction pins or a range of pins. The multi- a low input current to al ow direct sensor connection. Each input function pins, such as DCLK0/SDO, are referred to either by the channel has a programmable gain stage allowing gains of 1, 2, 4, entire pin name or by a single function of the pin, for example, and 8 to map lower amplitude sensor outputs into the ful -scale DCLK0, when only that function is relevant. In the case of ranges ADC input range, maximizing the dynamic range of the signal of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B, chain. The AD7770 accepts a VREF voltage from 1 V up to 3.6 V. AVSS2A, AVSS2B, AVSS3, and AVSS4.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7770 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIOx Pins Σ-Δ Reference Configuration Power Modes LDO Bypassing DIGITAL SPI SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-Δ Data, ADC Mode SPI Software Reset RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and Memory Map CRC Σ-Δ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7770 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) (-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header ERROR Header (SPI Control Mode) SRC (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay and Latency Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI CALCULATING THE CRC CHECKSUM Σ-Δ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE