Datasheet AD7172-4 (Analog Devices)
Manufacturer | Analog Devices |
Description | Low Power, with 4- or 8-channel, 24-bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
Pages / Page | 62 / 1 — Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta. ADC with True Rail-to-Rail … |
Revision | B |
File Format / Size | PDF / 862 Kb |
Document Language | English |
Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta. ADC with True Rail-to-Rail Buffers. Data Sheet. AD7172-4. FEATURES
Model Line for this Datasheet
Text Version of Document
Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Data Sheet AD7172-4 FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
The AD7172-4 is a low noise, low power, multiplexed, Σ-Δ analog-
Channel scan data rate of 6.21 kSPS/channel (161 μs settling)
to-digital converter (ADC) with 4- or 8-channel (fully differential/
Performance specifications
single-ended) inputs for low bandwidth signals. The AD7172-4
17.2 noise free bits at 31.25 kSPS
has a maximum channel scan rate of 6.21 kSPS (161 μs) for fully
24 noise free bits at 5 SPS
settled data. The output data rates range from 1.25 SPS to 31.25 kSPS.
INL: ±2 ppm of FSR
The AD7172-4 integrates key analog and digital signal condition-
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
ing blocks to allow users to configure an individual setup for
User configurable input channels
each analog input channel in use via the SPI. Integrated true rail-to-
4 fully differential channels or 8 single-ended channels
rail buffers on the analog inputs and reference inputs provide easy
Crosspoint multiplexer
to drive high impedance inputs.
True rail-to-rail analog and reference input buffers Internal or external clock
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
Power supply
at a 27.27 SPS output data rate. The user can switch between
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V
different filter options according to the demands of each channel
Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V
in the application, with further digital processing functions such
ADC current: 1.5 mA
as offset and gain calibration registers, which are configurable
Temperature range: −40°C to +105°C
on a per channel basis. General-purpose input/outputs (GPIOs)
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
control external multiplexers synchronous to the ADC conversion
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSP-
timing. The specified temperature range is −40°C to +105°C.
compatible
The AD7172-4 is in a 5 mm × 5 mm, 32-lead LFCSP.
APPLICATIONS
Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only.
Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ IOVDD REGCAPD CROSSPOINT 1.8V 1.8V MULTIPLEXER LDO RAIL-TO-RAIL LDO REFERENCE INPUT BUFFERS RAIL-TO-RAIL AIN0/REF2– AVDD ANALOG CS INPUT BUFFERS AIN1/REF2+ SCLK SERIAL DIN Σ-∆ ADC DIGITAL INTERFACE FILTER AND CONTROL DOUT/RDY SYNC AIN7 ERROR AVSS XTAL AND INTERNAL I/O AND EXTERNAL AIN8 CLOCK OSCILLATOR MUX CONTROL CIRCUITRY AD7172-4
1 00 6-
AVSS PDSW GPIO0 GPIO1 GPO2 GPO3 XTAL1 XTAL2/CLKIO DGND
67 12 Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-4 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-4 REFERENCE BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 7 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE