Datasheet AD7124-4 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference |
| Pages / Page | 92 / 4 — Data Sheet. AD7124-4. REVISION HISTORY. 7/2016—Rev. B to Rev. C. … |
| Revision | D |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
Data Sheet. AD7124-4. REVISION HISTORY. 7/2016—Rev. B to Rev. C. 12/2015—Rev. A to Rev. B. 7/2015—Rev. 0 to Rev. A
Model Line for this Datasheet
Text Version of Document
link to page 85 link to page 87 link to page 87 link to page 89 link to page 90 link to page 91 link to page 91 link to page 92 link to page 92
Data Sheet AD7124-4
ERROR_EN Register .. 84 Offset Registers .. 90 MCLK_COUNT Register .. 86 Gain Registers .. 90 Channel Registers .. 86 Outline Dimensions .. 91 Configuration Registers ... 88 Ordering Guide ... 91 Filter Registers ... 89
REVISION HISTORY 7/2016—Rev. B to Rev. C 12/2015—Rev. A to Rev. B
Change to Features Section .. 1 Changed +105°C to +125°C ... Throughout Changes to Specifications Section and Table 2.. 5 Changes to Table 2 .. 5 Changes to Table 4 .. 13 Added Endnote 4, Table 2; Renumbered Sequentially ... 10 Change to Table 8 .. 27 Changes to Figure 17 Through Figure 22 .. 18 Changes to Table 9 and Table 10 ... 28 Changes to Figure 23 Through Figure 26 .. 19 Change to Table 25 .. 32 Changes to Figure 30, Figure 33, and Figure 34 ... 20 Changes to Table 28 .. 33 Changes to Figure 37 Through Figure 40 .. 21 Change to Table 29 .. 34 Changes to Figure 41 Through Figure 46 .. 22 Changes to Accessing the ADC Register Map and Table 38 ... 38 Changes to Figure 47 and Figure 48 ... 23 Changes to Diagnostics Section, Table 44, and Table 45 ... 41 Changes to Figure 64 .. 25 Added External Impedance When Using a Gain of 1 Section, Changes to Figure 126 .. 69 Figure 74, Figure 75, and Figure 76; Renumbered Sequentially ... 45 Change to Table 17 .. 30 Changes to Standby and Power-Down Modes Section .. 48 Changes to Reference Section ... 36 Changes to Single Conversion Mode Section .. 50 Changes to Accessing the ADC Register Map Section and Changes to Continuous Read Mode Section ... 51 Table 38 ... 38 Changes to Sinc4 Output Data Rate/Settling Time Section ... 54 Change to Table 63 .. 76 Changes to Sinc4 Zero Latency Section .. 55 Change to ID Register Section .. 82 Changes to Sinc3 Output Data Rate and Settling Time Section .. 56 Change to Table 73 .. 85 Changes to Sinc3 Zero Latency Section .. 57 Change to Table 73 .. 86 Change to Output Data Rate and Settling Time, Sinc4 + Sinc1 Changes to the Ordering Guide .. 90 Filter Section .. 59 Change to Output Data Rate and Settling Time, Sinc3 + Sinc1
7/2015—Rev. 0 to Rev. A
Filter Section .. 60 Change to Data Sheet Title .. 1 Changes to SPI_IGNORE Error Section .. 68 Changes to Internal Reference Drift Parameter, Table 2 ... 7 Added ROM Checksum Protection Section .. 69 Changes to Figure 30 .. 20 Changes to Table 63 .. 77 Change to Digital Outputs Section ... 37 Changes to ID Register Section and Error Register Section ... 83 Change to Single Conversion Mode Section ... 49 Changes to Table 70 and ERROR_EN Register Section... 84 Changes to Calibration Section ... 51 Changes to Table 71 .. 85 Changes to Figure 83 .. 53 Changes to Table 73 .. 87 Changes to Figure 91 .. 56 Changes to Figure 99 .. 58 Changes to Figure 105 .. 60 Changes to Reference Detect Section and Figure 119 .. 65 Change to Table 70 .. 83 Changes to Table 71 .. 84
5/2015—Revision 0: Initial Version
Rev. C | Page 3 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7124-4
ERROR_EN Register .. 84 Offset Registers .. 90 MCLK_COUNT Register .. 86 Gain Registers .. 90 Channel Registers .. 86 Outline Dimensions .. 91 Configuration Registers ... 88 Ordering Guide ... 91 Filter Registers ... 89
REVISION HISTORY 7/2016—Rev. B to Rev. C 12/2015—Rev. A to Rev. B
Change to Features Section .. 1 Changed +105°C to +125°C ... Throughout Changes to Specifications Section and Table 2.. 5 Changes to Table 2 .. 5 Changes to Table 4 .. 13 Added Endnote 4, Table 2; Renumbered Sequentially ... 10 Change to Table 8 .. 27 Changes to Figure 17 Through Figure 22 .. 18 Changes to Table 9 and Table 10 ... 28 Changes to Figure 23 Through Figure 26 .. 19 Change to Table 25 .. 32 Changes to Figure 30, Figure 33, and Figure 34 ... 20 Changes to Table 28 .. 33 Changes to Figure 37 Through Figure 40 .. 21 Change to Table 29 .. 34 Changes to Figure 41 Through Figure 46 .. 22 Changes to Accessing the ADC Register Map and Table 38 ... 38 Changes to Figure 47 and Figure 48 ... 23 Changes to Diagnostics Section, Table 44, and Table 45 ... 41 Changes to Figure 64 .. 25 Added External Impedance When Using a Gain of 1 Section, Changes to Figure 126 .. 69 Figure 74, Figure 75, and Figure 76; Renumbered Sequentially ... 45 Change to Table 17 .. 30 Changes to Standby and Power-Down Modes Section .. 48 Changes to Reference Section ... 36 Changes to Single Conversion Mode Section .. 50 Changes to Accessing the ADC Register Map Section and Changes to Continuous Read Mode Section ... 51 Table 38 ... 38 Changes to Sinc4 Output Data Rate/Settling Time Section ... 54 Change to Table 63 .. 76 Changes to Sinc4 Zero Latency Section .. 55 Change to ID Register Section .. 82 Changes to Sinc3 Output Data Rate and Settling Time Section .. 56 Change to Table 73 .. 85 Changes to Sinc3 Zero Latency Section .. 57 Change to Table 73 .. 86 Change to Output Data Rate and Settling Time, Sinc4 + Sinc1 Changes to the Ordering Guide .. 90 Filter Section .. 59 Change to Output Data Rate and Settling Time, Sinc3 + Sinc1
7/2015—Rev. 0 to Rev. A
Filter Section .. 60 Change to Data Sheet Title .. 1 Changes to SPI_IGNORE Error Section .. 68 Changes to Internal Reference Drift Parameter, Table 2 ... 7 Added ROM Checksum Protection Section .. 69 Changes to Figure 30 .. 20 Changes to Table 63 .. 77 Change to Digital Outputs Section ... 37 Changes to ID Register Section and Error Register Section ... 83 Change to Single Conversion Mode Section ... 49 Changes to Table 70 and ERROR_EN Register Section... 84 Changes to Calibration Section ... 51 Changes to Table 71 .. 85 Changes to Figure 83 .. 53 Changes to Table 73 .. 87 Changes to Figure 91 .. 56 Changes to Figure 99 .. 58 Changes to Figure 105 .. 60 Changes to Reference Detect Section and Figure 119 .. 65 Change to Table 70 .. 83 Changes to Table 71 .. 84
5/2015—Revision 0: Initial Version
Rev. C | Page 3 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE
