Datasheet AD7981 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | High Temperature, 16-Bit, 600 kSPS PulSAR ADC |
| Pages / Page | 26 / 5 — Data Sheet. AD7981. TIMING SPECIFICATIONS. Table 3. Parameter. Symbol. … |
| Revision | B |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
Data Sheet. AD7981. TIMING SPECIFICATIONS. Table 3. Parameter. Symbol. Min. Typ. Max. Unit. Y% VIO1. 500µA. IOL. X% VIO1. tDELAY. V 2. TO SDO. 1.4V. 20pF
Model Line for this Datasheet
Text Version of Document
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Data Sheet AD7981 TIMING SPECIFICATIONS
VDD = 2.375 V to 2.625 V, VIO = 3.3 V to 5.5 V, TMIN to TMAX, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND ACQUISITION TIMES Conversion Time: CNV Rising Edge to Data Available tCONV 800 1200 ns Acquisition Time tACQ 290 ns Time Between Conversions tCYC 1667 ns CNV PULSE WIDTH (CS MODE) tCNVH 10 ns SCK SCK Period (CS Mode) tSCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CS MODE CNV or SDI Low to SDO D15 MSB Valid tEN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV 2 ns CHAIN MODE SDI Valid Hold Time from CNV Rising Edge tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns
Y% VIO1 500µA IOL X% VIO1 tDELAY tDELAY V 2 IH V 2 TO SDO 1.4V IH 2 2 C V V IL IL L 20pF 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
002
2
003
500µA I MINIMUM V OH IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
12479-
SPECIFICATIONS IN TABLE 2.
12479- Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 26 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUT DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE \CS MODE, 3-WIRE WITHOUT A BUSY INDICATOR \CS MODE, 3-WIRE WITH A BUSY INDICATOR \CS MODE, 4-WIRE WITHOUT A BUSY INDICATOR \CS MODE, 4-WIRE WITH A BUSY INDICATOR CHAIN MODE WITHOUT A BUSY INDICATOR CHAIN MODE WITH A BUSY INDICATOR APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7981 TIMING SPECIFICATIONS
VDD = 2.375 V to 2.625 V, VIO = 3.3 V to 5.5 V, TMIN to TMAX, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND ACQUISITION TIMES Conversion Time: CNV Rising Edge to Data Available tCONV 800 1200 ns Acquisition Time tACQ 290 ns Time Between Conversions tCYC 1667 ns CNV PULSE WIDTH (CS MODE) tCNVH 10 ns SCK SCK Period (CS Mode) tSCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CS MODE CNV or SDI Low to SDO D15 MSB Valid tEN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV 2 ns CHAIN MODE SDI Valid Hold Time from CNV Rising Edge tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns
Y% VIO1 500µA IOL X% VIO1 tDELAY tDELAY V 2 IH V 2 TO SDO 1.4V IH 2 2 C V V IL IL L 20pF 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
002
2
003
500µA I MINIMUM V OH IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
12479-
SPECIFICATIONS IN TABLE 2.
12479- Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 26 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUT DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE \CS MODE, 3-WIRE WITHOUT A BUSY INDICATOR \CS MODE, 3-WIRE WITH A BUSY INDICATOR \CS MODE, 4-WIRE WITHOUT A BUSY INDICATOR \CS MODE, 4-WIRE WITH A BUSY INDICATOR CHAIN MODE WITHOUT A BUSY INDICATOR CHAIN MODE WITH A BUSY INDICATOR APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
