Datasheet HMCAD5831LP9BE (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 26 GS/s 3-Bit Analog-to-Digital Converter w/ Overrange, Inhibit, and 1:2 DEMUX |
| Pages / Page | 15 / 10 — HMCAD5831LP9BE. 3-BIT 26 GSPS ANALOG-TO-DIGITAL. CONVERTER W/ OVERRANGE, … |
| File Format / Size | PDF / 939 Kb |
| Document Language | English |
HMCAD5831LP9BE. 3-BIT 26 GSPS ANALOG-TO-DIGITAL. CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX. Application Information
Model Line for this Datasheet
Text Version of Document
HMCAD5831LP9BE
v02.0713
3-BIT 26 GSPS ANALOG-TO-DIGITAL CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX Application Information
t
Reference Ladder
M s the aDC’s voltage reference ladder comprises 8, 18 Ω resistors, or 144 Ω total nominal resistance. Pin 1, rtF, and pin 15, rBF, are provided for the top and bottom reference taps. these pins are driven by external supplies to establish the desired ful -scale range of the aDC. the rF signal input (pin 8, In) to the aDC, which is nominal y centered at s - 0v (aGnD), drives an internal emitter fol ower with a nominal vBe of -936 mv. Hence the center of ful -scale range r should center near -936 mv. the voltage at pin rtF is then -936 mv + v /2. Likewise the voltage at pin rBF is full-scale e -936 mv - v /2. full-scale t as an example, if the user had a peak-to-peak input voltage swing of 256 mv centered at 0v and required the ful -scale r input range of the aDC to be 256 mv as wel , rtF would be -936 mv + 128 mv = -772 mv. rBF would be -936 mv - 128 mv = e -1.028v. note that the diode drop, -936 mv, is dependent on temperature and process variations. rtF and rBF values v in the “electrical specifications” table on pages 1 and 2 are shown as nominal values only. n o
Input Signal
the rF input is internal y terminated with 50 ohms to aGnD, which should be the system rF ground. normal y, the input signal is expected to have a common-mode point at this 0v point. Because this device al ows the user to set the top and bottom voltages of the reference ladder inside the device, the user has significant flexibility in adjusting the ata C aDC span and thus the ful -scale signal amplitude as well as the input signal’s common-mode point. D However, it is very important to notice that there are absolute voltage level limits on the peak input signal voltage. these are indicated in the operating Conditions table in this document. For proper operation of the device, the input signal must never swing higher than the vinput-max or lower than vinput-min voltages indicated in the operating Conditions table. the user is cautioned to also pay attention to the absolute Maximum ratings table as it lists the maximum input voltage beyond which damage to the device will result.
VREF Pins
Pins 26 and 55 (vreF1 and vreF2) should be connected together off chip and the pair is then connected to the oGnD through a resistor. these pins are used to vary the output swing voltage. the application Circuit shown uses a 200 Ω resistor. this provides the typical output swings listed in the electrical specifications table. Increasing the voltage on vreF1 and vreF2 will increase the output swing. Conversely, decreasing the vreF1 and vreF2 voltages will decrease the output swing.
Overrange Output
Pins 28, 29, 31, and 32 provide overrange output bits. this function indicates when the input signal is out of range of the reference ladder voltages. the bit will be high when either the signal is above rtF or below rBF. the overrange bit is cleared for the next clock cycle containing in-range data.
Data Inhibit
all data outputs can be forced to “0” by enabling the Data Inhibit function (pins 61 and 62). By driving the QtP pin high and the Qtn pin low, the aDC core will produce all 0s. this occurs prior to the Xor function and the demux. When QtP is low and Qtn is high, the chip operates normal y, and these inputs must be set this way for normal operation. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
9
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 pp3li o ca rti a o pp n Susp@h portitti : P te ho .c neom : 1-800-ANALOG-D
v02.0713
3-BIT 26 GSPS ANALOG-TO-DIGITAL CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX Application Information
t
Reference Ladder
M s the aDC’s voltage reference ladder comprises 8, 18 Ω resistors, or 144 Ω total nominal resistance. Pin 1, rtF, and pin 15, rBF, are provided for the top and bottom reference taps. these pins are driven by external supplies to establish the desired ful -scale range of the aDC. the rF signal input (pin 8, In) to the aDC, which is nominal y centered at s - 0v (aGnD), drives an internal emitter fol ower with a nominal vBe of -936 mv. Hence the center of ful -scale range r should center near -936 mv. the voltage at pin rtF is then -936 mv + v /2. Likewise the voltage at pin rBF is full-scale e -936 mv - v /2. full-scale t as an example, if the user had a peak-to-peak input voltage swing of 256 mv centered at 0v and required the ful -scale r input range of the aDC to be 256 mv as wel , rtF would be -936 mv + 128 mv = -772 mv. rBF would be -936 mv - 128 mv = e -1.028v. note that the diode drop, -936 mv, is dependent on temperature and process variations. rtF and rBF values v in the “electrical specifications” table on pages 1 and 2 are shown as nominal values only. n o
Input Signal
the rF input is internal y terminated with 50 ohms to aGnD, which should be the system rF ground. normal y, the input signal is expected to have a common-mode point at this 0v point. Because this device al ows the user to set the top and bottom voltages of the reference ladder inside the device, the user has significant flexibility in adjusting the ata C aDC span and thus the ful -scale signal amplitude as well as the input signal’s common-mode point. D However, it is very important to notice that there are absolute voltage level limits on the peak input signal voltage. these are indicated in the operating Conditions table in this document. For proper operation of the device, the input signal must never swing higher than the vinput-max or lower than vinput-min voltages indicated in the operating Conditions table. the user is cautioned to also pay attention to the absolute Maximum ratings table as it lists the maximum input voltage beyond which damage to the device will result.
VREF Pins
Pins 26 and 55 (vreF1 and vreF2) should be connected together off chip and the pair is then connected to the oGnD through a resistor. these pins are used to vary the output swing voltage. the application Circuit shown uses a 200 Ω resistor. this provides the typical output swings listed in the electrical specifications table. Increasing the voltage on vreF1 and vreF2 will increase the output swing. Conversely, decreasing the vreF1 and vreF2 voltages will decrease the output swing.
Overrange Output
Pins 28, 29, 31, and 32 provide overrange output bits. this function indicates when the input signal is out of range of the reference ladder voltages. the bit will be high when either the signal is above rtF or below rBF. the overrange bit is cleared for the next clock cycle containing in-range data.
Data Inhibit
all data outputs can be forced to “0” by enabling the Data Inhibit function (pins 61 and 62). By driving the QtP pin high and the Qtn pin low, the aDC core will produce all 0s. this occurs prior to the Xor function and the demux. When QtP is low and Qtn is high, the chip operates normal y, and these inputs must be set this way for normal operation. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
9
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 pp3li o ca rti a o pp n Susp@h portitti : P te ho .c neom : 1-800-ANALOG-D
