Datasheet AD9652 (Analog Devices)

16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9652 FEATURES FUNCTIONAL BLOCK DIAGRAM High dynamic range AVDD3 AVDD SDIO SCLK CSB DRVDD SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS) SFDR = 87 dBc at 70 MHz (A SPI IN = −1 dBFS) AD9652 Noise spectral density (NSD) = −156.7 dBFS/Hz input noise at −1 dBFS at 70 MHz PROGRAMMING DATA OR+, OR– NSD = −157.6 dBFS/Hz for small signal at −7dBFS at 70 MHz VIN+A DDR DATA D15± (MSB) 90 dB channel isolation/crosstalk ADC INTERLEAVER 16 TO VIN–A LVDS OUTPUT D0± (LSB)* On-chip dithering (improves small signal linearity) DRIVER Excellent IF sampling performance VREF SNR = 73.7 dBFS at 170 MHz (A CLK+ IN = −1 dBFS) DIVIDE 1 TO 8 SFDR = 85 dBc at 170 MHz (A SENSE CLK– IN = −1 dBFS) Full power bandwidth of 465 MHz REF DUTY CYCLE DCO DCO+ On-chip 3.3 V buffer SELECT VCM STABILIZER GENERATION DCO– Programmable input span of 2 V p-p to 2.5 V p-p (default) RBIAS Differential clock input receiver with 1, 2, 4, and 8 integer VIN–B inputs (clock divider input accepts up to 1.24 GHz) ADC MULTICHIP Internal ADC clock duty cycle stabilizer VIN+B SYNC SYNC input allows multichip synchronization Total power consumption: 2.16 W AGND SYNC PDWN
01 0 9-
3.3 V and 1.8 V supply voltages *THESE PINS ARE FOR CHANNEL A AND CHANNEL B.
216 1
DDR LVDS (ANSI-644 levels) outputs
Figure 1.
Serial port control Energy saving power-down modes APPLICATIONS Military radar and communications Multimode digital receivers (3G or 4G) Test and instrumentation Smart antenna systems GENERAL DESCRIPTION
The 16-bit output data (with an overrange bit) from each ADC The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) is interleaved onto a single LVDS output port along with a with sampling speeds of up to 310 MSPS. It is designed to double data rate (DDR) clock. Programming for setup and control support demanding, high speed signal processing applications are accomplished using a 3-wire SPI-compatible serial interface. that require exceptional dynamic range over a wide input The AD9652 is available in a 144-ball CSP_BGA and is frequency range (up to 465 MHz). Its exceptional low noise specified over the industrial temperature range of −40°C to floor of −157.6 dBFS and large signal spurious-free dynamic +85°C. This product is protected by pending U.S. patents. range (SFDR) performance (exceeding 85 dBFS, typical) allows
PRODUCT HIGHLIGHTS
low level signals to be resolved in the presence of large signals. 1. Integrated dual, 16-bit, 310 MSPS ADCs. The dual ADC cores feature a multistage, pipelined architecture 2. On-chip buffer simplifies ADC driver interface. with integrated output error correction logic. A high performance 3. Operation from 3.3 V and 1.8 V supplies and a separate on-chip buffer and internal voltage reference simplify the inter- digital output driver supply accommodating LVDS outputs. face to external driving circuitry while preserving the exceptional 4. Proprietary differential input maintains excellent signal-to- performance of the ADC. noise ratio (SNR) performance for input frequencies of up The AD9652 can support input clock frequencies of up to to 485 MHz. 1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate 5. SYNC input allows synchronization of multiple devices. the ADC sample clock. A duty cycle stabilizer is provided to 6. Three-wire, 3.3 V or 1.8 V SPI port for register programming compensate for variations in the ADC clock duty cycle. and readback.
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Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide