Datasheet AD9656 (Analog Devices)

Quad, 16-Bit, 125 MSPS, JESD204B 1.8 V Analog-to-Digital Converter Data Sheet AD9656 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 79.9 dBFS at 16 MHz (V AVDD PDWN DVDD DRVDD REF = 1.4 V) SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V) VINA+ 16 SERDOUT0+ SFDR = 86 dBc to Nyquist (V PIPELINE JESD204B REF = 1.4 V) VINA– ADC INTERFACE SERDOUT0– JESD204B Subclass 1 coded serial digital outputs SERDOUT1+ VINB+ 16 Flexible analog input range: 2.0 V p-p to 2.8 V p-p PIPELINE CML TX SERDOUT1– VINB– ADC OUTPUTS SERDOUT2+ 1.8 V supply operation RBIAS SERDOUT2– Low power: 197 mW per channel at 125 MSPS (two lanes) VREF SERDOUT3+ SENSE HIGH 1V DNL = ±0.6 LSB (V SPEED SERDOUT3– REF = 1.4 V) REF TO SERIALIZERS SELECT 1.4V SYNCINB+ INL = ±4.5 LSB (VREF = 1.4 V) AGND SYNCINB– 650 MHz analog input bandwidth, full power VINC+ 16 PIPELINE Serial port control VINC– ADC Full chip and individual channel power-down modes CONTROL VIND+ 16 PIPELINE REGISTERS Built-in and custom digital test pattern generation VIND– ADC Multichip sync and clock divider SERIAL PORT Standby mode CLOCK AD9656 VCM INTERFACE MANAGEMENT APPLICATIONS K D C / +/ – – IO L D K+ K Medical ultrasound and MRI CSB EF EF VSS SD SC
1
SV SYN CL CL D SR
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High speed imaging SY SYSR
868 1 1
Quadrature radio receivers
Figure 1.
Diversity radio receivers
The AD9656 is available in an RoHS compliant, nonmagnetic,
Portable test equipment
56-lead LFCSP. It is specified over the −40°C to +85°C industrial temperature range.
GENERAL DESCRIPTION
The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital
PRODUCT HIGHLIGHTS
converter (ADC) with an on-chip sample and hold circuit 1. It has a small footprint. Four ADCs are contained in a small, designed for low cost, low power, small size, and ease of use. 8 mm × 8 mm package. The device operates at a conversion rate of up to 125 MSPS and 2. An on-chip phase-locked loop (PLL) allows users to provide is optimized for outstanding dynamic performance and low a single ADC sampling clock; the PLL multiplies the ADC power in applications where a small package size is critical. sampling clock to produce the corresponding JESD204B The ADC requires a single 1.8 V power supply and LVPECL-/ data rate clock. CMOS-/LVDS-compatible sample rate clock for full performance 3. The configurable JESD204B output block supports up to operation. An external reference or driver components are not 8.0 Gbps per lane. required for many applications. 4. JESD204B output block supports one, two, and four lane configurations. Individual channel power-down is supported and typically 5. Low power of 198 mW per channel at 125 MSPS, two lanes. consumes less than 14 mW when all channels are disabled. The 6. The SPI control offers a wide range of flexible features to ADC contains several features designed to maximize flexibility meet specific system requirements. and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudo- random patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS, VREF = 1.4 V DC SPECIFICATIONS, VREF = 1.0 V AC SPECIFICATIONS, VREF = 1.4 V AC SPECIFICATIONS, VREF = 1.0 V DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.4 V VREF = 1.0 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common-Mode Voltage Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS JESD204B Transmit Top Level Description JESD204B Overview JESD204B Configurations Initial JESD204B Link Startup Resynchronization JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bit 5—PDWN Pin Function Bit 4—JTX Standby Mode Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bit 2—Chop Mode Output Mode (Register 0x14) Bits[7:5]—JTX CS Mode Bits[1:0]—Output Format Clock Phase Control (Register 0x16) Bits[6:4]—Input Clock Phase Adjust JTX User Pattern (Register 0xA0 to Register 0xA7) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE