Datasheet AD9249 (Analog Devices) - 5

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AD9249 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1. Parameter1 Temp Min Typ Max Unit
RESOLUTION 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full 0 0.24 0.8 % FSR Offset Matching Full 0 0.24 0.7 % FSR Gain Error Full −7.2 −3.5 +0.2 % FSR Gain Matching Full 0 1.8 6.0 % FSR Differential Nonlinearity (DNL) Full −0.9 ±0.6 +1.6 LSB Integral Nonlinearity (INL) Full −3.0 ±0.9 +3.0 LSB TEMPERATURE DRIFT Offset Error Full −1.8 ppm/°C Gain Error Full 3.6 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.0 1.01 V Load Regulation at 1.0 mA (VREF = 1 V) 25°C 3 mV Input Resistance Full 7.5 kΩ INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.98 LSB rms ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 V p-p Common-Mode Voltage Full 0.9 V Common-Mode Range Full 0.5 1.3 V Differential Input Resistance Full 5.2 kΩ Differential Input Capacitance Full 3.5 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD Full 395 429 mA IDRVDD (ANSI-644 Mode) Full 118 124 mA IDRVDD (Reduced Range Mode) 25°C 88 mA TOTAL POWER CONSUMPTION Total Power Dissipation (16 Channels, ANSI-644 Mode) Full 924 995 mW Total Power Dissipation (16 Channels, Reduced Range Mode) 25°C 869 mW Power-Down Dissipation 25°C 2 mW Standby Dissipation2 25°C 199 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for information about how these tests were completed. 2 Controlled via the SPI. Rev. 0 | Page 4 of 36 Document Outline Features Applications General Description Simplified Functional Block Diagram Product Highlights Revision History Functional Block Diagram Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Timing Specifications SYNC Timing Diagram Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel Specific Registers Memory Map Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—FCO±x, DCO±x Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Board Layout Considerations Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock Clock Stability Considerations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide