Datasheet AD7961 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 16-Bit, 5 MSPS PULSAR® Differential ADC |
| Pages / Page | 25 / 7 — AD7961. Data Sheet. Timing Diagrams. SAMPLE N. SAMPLE N + 1. tCYC. tCNVH. … |
| Revision | B |
| File Format / Size | PDF / 629 Kb |
| Document Language | English |
AD7961. Data Sheet. Timing Diagrams. SAMPLE N. SAMPLE N + 1. tCYC. tCNVH. CNV–. CNV+. tACQ. ACQUISITION. tCLKL. tCLK. CLK–. CLK+. tDCO. DCO–. DCO+. tMSB
Model Line for this Datasheet
Text Version of Document
AD7961 Data Sheet Timing Diagrams SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 15 16 1 2 15 16 1 2 3 CLK– CLK+ tDCO 15 16 1 2 15 16 1 2 3 DCO– DCO+ tMSB t t D CLKD D+ D1 D0 D15 D14 D1 D0 D15 D14 0 D13
002
N – 1 N – 1 0 N N N N N + 1 N + 1 N + 1 D–
10888- Figure 2. Echoed Clock Interface Mode Timing Diagram
SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 17 18 1 2 3 4 17 18 1 2 3 CLK– CLK+ t t MSB CLKD D+ D1 D0 D15 D14 D1 D0 D15
003
0 1 0 0 1 0 N – 1 N – 1 N N N N N + 1 D–
10888- Figure 3. Self-Clocked Interface Mode Timing Diagram Rev. B | Page 6 of 24 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Information Transfer Function Analog Inputs Typical Applications Voltage Reference Options Wake-Up Time from Power-Down and Snooze Modes Power Supply Power-Up Digital Interface Conversion Control Echoed Clock Interface Mode Self Clocked Mode Applications Information Layout Evaluating AD7961 Performance Outline Dimensions Ordering Guide
002
N – 1 N – 1 0 N N N N N + 1 N + 1 N + 1 D–
10888- Figure 2. Echoed Clock Interface Mode Timing Diagram
SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 17 18 1 2 3 4 17 18 1 2 3 CLK– CLK+ t t MSB CLKD D+ D1 D0 D15 D14 D1 D0 D15
003
0 1 0 0 1 0 N – 1 N – 1 N N N N N + 1 D–
10888- Figure 3. Self-Clocked Interface Mode Timing Diagram Rev. B | Page 6 of 24 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Information Transfer Function Analog Inputs Typical Applications Voltage Reference Options Wake-Up Time from Power-Down and Snooze Modes Power Supply Power-Up Digital Interface Conversion Control Echoed Clock Interface Mode Self Clocked Mode Applications Information Layout Evaluating AD7961 Performance Outline Dimensions Ordering Guide
