Datasheet ADAS3023 (Analog Devices) - 6

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Data Sheet ADAS3023 Parameter Test Conditions/Comments Min Typ Max Unit1
IVDDH Two channels 5.0 5.5 mA Four channels 6.0 7.0 mA Six channels 9.5 10.5 mA Eight channels 9.5 10.5 mA PD = 1 10.0 µA IVSSH Two channels −5.5 −5.0 mA Four channels −6.5 −5.5 mA Six channels −10.0 −8.5 mA Eight channels −10.0 −8.5 mA All PGIA gains, PD = 1 10.0 µA IAVDD All PGIA gains, PD = 0, reference buffer enabled 16.0 17.0 mA All PGIA gains, PD = 0, reference buffer disabled 15.5 mA All PGIA gains, PD = 1 100 µA IDVDD All PGIA gains, PD = 0 2.5 3 mA All PGIA gains, PD = 1 100 µA IVIO All PGIA gains, PD = 0, VIO = 3.3 V 1.0 mA All PGIA gains, PD = 1 10.0 µA Power Supply Sensitivity External reference, TA = 25°C PGIA gain = 0.2 or 0.4, VDDH/VSSH = ±15 V ± 5% ±0.1 LSB PGIA gain = 0.8, VDDH/VSSH = ±15 V ± 5% ±0.2 LSB PGIA gain = 1.6, VDDH/VSSH = ±15 V ± 5% ±0.4 LSB PGIA gain = 0.2 or 0.4, AVDD, DVDD = ±5 V ± 5% ±1.0 LSB PGIA gain = 0.8, AVDD, DVDD = ±5 V ± 5% ±1.5 LSB PGIA gain = 1.6, AVDD, DVDD = ±5 V ± 5% ±2.5 LSB TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 The LSB unit means least significant bit. The weight of the LSB, referred to input, changes depending on the input voltage range. See the Programmable Gain section for the LSB size. 2 Full-scale differential input ranges of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V are set by the configuration register. 3 If using the external multiplexer in front of the ADAS3023, it must be switched at least 820 ns prior to the rising edge of CNV. 4 See the Terminology section. These parameters are specified at ambient temperature with an external reference. All other influences of temperature and supply are measured and specified separately. 5 All ac specifications expressed in decibels are referenced to the full-scale input range (FSR) and are tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 6 This is the output from the internal band gap reference. 7 There is no pipeline delay. Conversion results are available immediately after a conversion is completed. Rev. A | Page 5 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide