Datasheet AD7175-8 (Analog Devices) - 3

ManufacturerAnalog Devices
Description24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers
Pages / Page65 / 3 — AD7175-8. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 10/15—Revision …
File Format / SizePDF / 1.1 Mb
Document LanguageEnglish

AD7175-8. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 10/15—Revision 0: Initial Version

AD7175-8 Data Sheet TABLE OF CONTENTS REVISION HISTORY 10/15—Revision 0: Initial Version

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AD7175-8 Data Sheet TABLE OF CONTENTS
Features .. 1 CRC Calculation ... 41 Applications ... 1 Integrated Functions .. 43 General Description ... 1 General-Purpose I/O ... 43 Functional Block Diagram .. 1 External Multiplexer Control ... 43 Revision History ... 2 Delay .. 43 Specifications ... 3 16-Bit/24-Bit Conversions... 43 Timing Characteristics .. 6 DOUT_RESET ... 43 Absolute Maximum Ratings .. 8 Synchronization .. 43 Thermal Resistance .. 8 Error Flags ... 44 ESD Caution .. 8 DATA_STAT ... 44 Pin Configuration and Function Descriptions ... 9 IOSTRENGTH ... 44 Typical Performance Characteristics ... 11 Power-Down Switch .. 45 Noise Performance and Resolution .. 17 Internal Temperature Sensor .. 45 Getting Started .. 18 Grounding and Layout .. 46 Power Supplies .. 19 Register Summary .. 47 Digital Communication ... 19 Register Details ... 49 AD7175-8 Reset .. 20 Communications Register ... 49 Configuration Overview ... 20 Status Register ... 51 Circuit Description ... 25 ADC Mode Register ... 52 Buffered Analog Input ... 25 Interface Mode Register .. 53 Crosspoint Multiplexer .. 25 Register Check .. 54 AD7175-8 Reference .. 26 Data Register ... 54 Buffered Reference Input ... 27 GPIO Configuration Register ... 55 Clock Source ... 27 ID Register... 56 Digital Filters ... 28 Channel Register 0 ... 56 Sinc5 + Sinc1 Filter... 28 Channel Register 1 to Channel Register 15 .. 58 Sinc3 Filter ... 28 Setup Configuration Register 0 .. 59 Single Cycle Settling ... 29 Setup Configuration Register 1 to Setup Configuration Register 7 ... 60 Enhanced 50 Hz and 60 Hz Rejection Filters ... 33 Filter Configuration Register 0 ... 61 Operating Modes .. 36 Filter Configuration Register 1 to Filter Configuration Continuous Conversion Mode ... 36 Register 7 ... 62 Continuous Read Mode ... 37 Offset Register 0 ... 62 Single Conversion Mode ... 38 Offset Register 1 to Offset Register 7 ... 62 Standby and Power-Down Modes .. 39 Gain Register 0.. 62 Calibration ... 39 Gain Register 1 to Gain Register 7 ... 63 Digital Interface .. 40 Outline Dimensions ... 64 Checksum Protection... 40 Ordering Guide .. 64
REVISION HISTORY 10/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE