Datasheet AD9434 (Analog Devices)

12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9434 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 65 dBFS at f VREF PWDN AGND AVDD IN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS) SFDR = 78 dBc at f REFERENCE AD9434 IN up to 250 MHz at 500 MSPS (−1.0 dBFS) Integrated input buffer CML DRVDD Excellent linearity DRGND VIN+ TRACK-AND-HOLD DNL = ±0.5 LSB typical VIN– ADC 12 OUTPUT 12 INL = ±0.6 LSB typical CORE STAGING D11± TO D0± LVDS LVDS at 500 MSPS (ANSI-644 levels) CLK+ CLOCK OR+ 1 GHz full power analog bandwidth CLK– MANAGEMENT OR– On-chip reference, no external decoupling required SERIAL PORT Low power dissipation DCO+ 690 mW at 500 MSPS—LVDS SDR mode DCO–
001
660 mW at 500 MSPS—LVDS DDR mode SCLK/DFS SDIO CSB
09383-
Programmable (nominal) input voltage range
Figure 1.
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment APPLICATIONS Wireless and wired broadband communications
Fabricated on an advanced BiCMOS process, the AD9434 is
Cable reverse path
available in a 56-lead LFCSP, specified over the industrial
Communications test equipment
temperature range (−40°C to +85°C). This part is protected
Radar and satellite subsystems
under a U.S. patent.
Power amplifier linearization PRODUCT HIGHLIGHTS GENERAL DESCRIPTION
1. High Performance. The AD9434is a 12-bit monolithic sampling analog-to-digital Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input. converter (ADC) optimized for high performance, low power, 2. Low Power. and ease of use. The part operates at up to a 500 MSPS Consumes only 660 mW at 500 MSPS. conversion rate and is optimized for outstanding dynamic 3. Ease of Use. performance in wideband carrier and broadband systems. All LVDS output data and output clock signal al ow interface necessary functions, including a sample-and-hold and voltage to FPGA technology. The on-chip reference and sample- reference, are included on the chip to provide a complete signal and-hold provide flexibility in system design. Use of a conversion solution. The VREF pin can be used to monitor the single 1.8 V supply simplifies system power supply design. internal reference or provide an external voltage reference 4. Serial Port Control. (external reference mode must be enabled through the SPI Standard serial port interface supports various product port). functions, such as data formatting, power-down, gain adjust, and output test pattern generation. The ADC requires a 1.8 V analog voltage supply and a differen- 5. The AD9434 is pin compatible with the AD9230, and can tial clock for full performance operation. The digital outputs are be substituted in many applications with minimal design LVDS (ANSI-644) compatible and support twos complement, changes. offset binary format, or Gray code. A data clock output is available for proper output data timing.
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide