Datasheet AD9434 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter |
| Pages / Page | 29 / 6 — Data Sheet. AD9434. DIGITAL SPECIFICATIONS. Table 3. AD9434-370. … |
| Revision | B |
| File Format / Size | PDF / 937 Kb |
| Document Language | English |
Data Sheet. AD9434. DIGITAL SPECIFICATIONS. Table 3. AD9434-370. AD9434-500. Parameter1. Temp. Min. Typ. Max. Unit
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Data Sheet AD9434 DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3. AD9434-370 AD9434-500 Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 −10 +10 µA Low Level Input Current (IIL) Full −10 +10 −10 +10 µA Input Resistance (Differential) Full 8 10 12 8 10 12 kΩ Input Capacitance Full 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × DRVDD 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 0 µA Logic 0 Input Current (SDIO, CSB) Full −60 −60 µA Logic 1 Input Current (SCLK, PDWN) Full 50 50 µA Logic 0 Input Current (SCLK, PDWN) Full 0 0 µA Input Capacitance 25°C 4 4 pF LOGIC OUTPUTS2 VOD Differential Output Voltage Full 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω. Rev. B | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide
Data Sheet AD9434 DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3. AD9434-370 AD9434-500 Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 −10 +10 µA Low Level Input Current (IIL) Full −10 +10 −10 +10 µA Input Resistance (Differential) Full 8 10 12 8 10 12 kΩ Input Capacitance Full 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × DRVDD 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 0 µA Logic 0 Input Current (SDIO, CSB) Full −60 −60 µA Logic 1 Input Current (SCLK, PDWN) Full 50 50 µA Logic 0 Input Current (SCLK, PDWN) Full 0 0 µA Input Capacitance 25°C 4 4 pF LOGIC OUTPUTS2 VOD Differential Output Voltage Full 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω. Rev. B | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide
