Datasheet AD9467 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter |
| Pages / Page | 34 / 9 — Data Sheet. AD9467. SWITCHING SPECIFICATIONS. Table 4. AD9467BCPZ-200. … |
| Revision | D |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
Data Sheet. AD9467. SWITCHING SPECIFICATIONS. Table 4. AD9467BCPZ-200. AD9467BCPZ-250. Parameter1. Temp. Min. Typ. Max. Unit. Timing Diagrams
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Text Version of Document
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Data Sheet AD9467 SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 4. AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK2 Clock Rate Full 50 200 50 250 MSPS Clock Pulse Width High (tCH) Full 2.5 2 ns Clock Pulse Width Low (tCL) Full 2.5 2 ns OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) 25°C 3 3 ns Rise Time (tR) (20% to 80%) 25°C 200 200 ps Fall Time (tF) (20% to 80%) 25°C 200 200 ps DCO Propagation Delay (tCPD) 25°C 3 3 ns DCO to Data Delay (tSKEW) Full −200 +200 −200 +200 ps Wake-Up Time (Power-Down) Full 100 100 ms Pipeline Latency Full 16 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1.2 1.2 ns Aperture Uncertainty (Jitter) 25°C 60 60 fs rms Out-of-Range Recovery Time 25°C 1 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR-4 material.
Timing Diagrams N – 1 N + 4 tA N + 5 N N + 3 VIN± N + 1 N + 2 tCH tCL 1/fs CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD D15–/D14– (MSB) D15 D14 N – 16 N – 16 N – 15 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 10 D15+/D14+ (MSB) . . D1–/D0– (LSB)
002
D1 D0 N – 16 N – 16 N – 15 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 10 D1+/D0+ (LSB)
09029- Figure 2. 16-Bit Output Data Timing Rev. D | Page 7 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations SFDR Optimization—Buffer Current Adjustment Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power Supplies Full-Scale and Reference Options Digital Outputs and Timing Overrange (OR) Output Pins SPI Pins: SCLK, SDIO, CSB Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide
Data Sheet AD9467 SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 4. AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK2 Clock Rate Full 50 200 50 250 MSPS Clock Pulse Width High (tCH) Full 2.5 2 ns Clock Pulse Width Low (tCL) Full 2.5 2 ns OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) 25°C 3 3 ns Rise Time (tR) (20% to 80%) 25°C 200 200 ps Fall Time (tF) (20% to 80%) 25°C 200 200 ps DCO Propagation Delay (tCPD) 25°C 3 3 ns DCO to Data Delay (tSKEW) Full −200 +200 −200 +200 ps Wake-Up Time (Power-Down) Full 100 100 ms Pipeline Latency Full 16 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1.2 1.2 ns Aperture Uncertainty (Jitter) 25°C 60 60 fs rms Out-of-Range Recovery Time 25°C 1 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR-4 material.
Timing Diagrams N – 1 N + 4 tA N + 5 N N + 3 VIN± N + 1 N + 2 tCH tCL 1/fs CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD D15–/D14– (MSB) D15 D14 N – 16 N – 16 N – 15 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 10 D15+/D14+ (MSB) . . D1–/D0– (LSB)
002
D1 D0 N – 16 N – 16 N – 15 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 10 D1+/D0+ (LSB)
09029- Figure 2. 16-Bit Output Data Timing Rev. D | Page 7 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations SFDR Optimization—Buffer Current Adjustment Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power Supplies Full-Scale and Reference Options Digital Outputs and Timing Overrange (OR) Output Pins SPI Pins: SCLK, SDIO, CSB Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide
