Datasheet AD9269 (Analog Devices) - 7

AD9269 Data Sheet AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 2. AD9269-20/AD9269-40 AD9269-65 AD9269-80 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 78.0 77.5 77.6 dBFS fIN = 30.5 MHz 25°C 77.5 77.5 77.2 dBFS Full 76.5 76.5 dBFS fIN = 70 MHz 25°C 76.5 76.5 76.3 dBFS Full 75.5 dBFS fIN = 200 MHz 25°C 71.0 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 77.9 77.4 77.4 dBFS fIN = 30.5 MHz 25°C 77.2 77.2 76.9 dBFS Full 76.0 76.0 dBFS fIN = 70 MHz 25°C 76.4 76.4 76.1 dBFS Full 75.0 dBFS fIN = 200 MHz 25°C 69.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.6 12.6 12.6 Bits fIN = 30.5 MHz 25°C 12.5 12.5 12.5 Bits fIN = 70 MHz 25°C 12.4 12.4 12.3 Bits fIN = 200 MHz 25°C 11.2 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −95 −97 −93 dBc fIN = 30.5 MHz 25°C −90 −93 −92 dBc Full −80 −80 dBc fIN = 70 MHz 25°C −89 −97 −90 dBc Full −80 dBc fIN = 200 MHz 25°C −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 90 91 92 dBc Full 80 80 dBc fIN = 70 MHz 25°C 89 95 90 dBc Full 80 dBc fIN = 200 MHz 25°C 80 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −99 −89 −99 dBc fIN = 30.5 MHz 25°C −100 −100 −99 dBc Full −90 −91 dBc fIN = 70 MHz 25°C −99 −100 −97 dBc Full −89 dBc fIN = 200 MHz 25°C −86 dBc TWO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc CROSSTALK2 Full −110 −110 −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. A | Page 6 of 40 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9269-80 AD9269-65 AD9269-40 AD9269-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB (Pin 47) Bits [6:4]—Open Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 1—Open Bit 0—Disable SDIO Pull-Down QEC Control 0 (Register 0x110) Bits[7:6]—Open Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain Bits[2:0]—DC Enable/Phase Enable/Gain Enable QEC Control 1 (Register 0x111) Bits[7:3]—Open Bit 2—Force DC Bit 1—Force Phase Bit 0—Force Gain QEC Gain Bandwidth Control (Register 0x112) Bits[7:5]—Open Bits[4:0]—KEXP_GAIN QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bits[4:0]—KEXP_PHASE QEC DC Bandwidth Control (Register 0x114) Bits[7:5]—Open Bits[4:0]—KEXP_DC QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and Register 0x117) Bits[14:0]—Initial Gain QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and Register 0x119) Bits[12:0]—Initial Phase QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and Register 0x11B) Bits[13:0]—Initial DC I QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and Register 0x11D) Bits[13:0]—Initial DC Q Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide