Datasheet AD9262 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC |
| Pages / Page | 33 / 9 — AD9262. ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL RESISTANCE. Parameter … |
| Revision | A |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD9262. ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL RESISTANCE. Parameter Rating. Table 7. Thermal Resistance. Package Type. θJC Unit
Model Line for this Datasheet
Text Version of Document
AD9262 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL RESISTANCE Parameter Rating
The exposed paddle must be soldered to the ground plane for Electrical the LFCSP package. Soldering the exposed paddle to the PCB AVDD to AGND −0.3 V to +2.0 V increases the reliability of the solder joints, maximizing the DVDD to DGND −0.3 V to +2.0 V thermal capability of the package. DRVDD to DGND −0.3 V to +3.9 V
Table 7. Thermal Resistance
AGND to DGND −0.3 V to +0.3 V
Package Type θ
AVDD to DRVDD −3.9 V to +2.0 V
JA θJC Unit
CVDD to CGND −0.3 V to +2.0 V 64-Lead LFCSP (CP-64-4) 21.2 1.1 °C/W CGND to DGND −0.3 V to +0.3 V Typical θJA and θJC are specified for a 4-layer board in still air. D0A to D15A to DGND −0.3 V to +2.0 V Airflow increases heat dissipation, effectively reducing θJA. In D0B to D15B to DGND −0.3 V to +2.0 V addition, metal in direct contact with the package leads from DCO to DGND −0.3 V to +2.0 V metal traces, through holes, ground, and power planes reduces ORA, ORB to DGND −0.3 V to +2.0 V the θJA. SDIO to DGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK to AGND −0.3 V to +3.9 V
ESD CAUTION
VIN+A/VIN−A, VIN+B/VIN−B to AGND −0.3 V to +2.5 V CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 Sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
The exposed paddle must be soldered to the ground plane for Electrical the LFCSP package. Soldering the exposed paddle to the PCB AVDD to AGND −0.3 V to +2.0 V increases the reliability of the solder joints, maximizing the DVDD to DGND −0.3 V to +2.0 V thermal capability of the package. DRVDD to DGND −0.3 V to +3.9 V
Table 7. Thermal Resistance
AGND to DGND −0.3 V to +0.3 V
Package Type θ
AVDD to DRVDD −3.9 V to +2.0 V
JA θJC Unit
CVDD to CGND −0.3 V to +2.0 V 64-Lead LFCSP (CP-64-4) 21.2 1.1 °C/W CGND to DGND −0.3 V to +0.3 V Typical θJA and θJC are specified for a 4-layer board in still air. D0A to D15A to DGND −0.3 V to +2.0 V Airflow increases heat dissipation, effectively reducing θJA. In D0B to D15B to DGND −0.3 V to +2.0 V addition, metal in direct contact with the package leads from DCO to DGND −0.3 V to +2.0 V metal traces, through holes, ground, and power planes reduces ORA, ORB to DGND −0.3 V to +2.0 V the θJA. SDIO to DGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK to AGND −0.3 V to +3.9 V
ESD CAUTION
VIN+A/VIN−A, VIN+B/VIN−B to AGND −0.3 V to +2.5 V CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 Sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
