Datasheet AD7193 (Analog Devices) - 4

Data Sheet AD7193 REVISION HISTORY 7/2017—Rev. D to Rev. E 9/2009—Rev. 0 to Rev. A
Changed CP-32-11 to CP-32-12 .. Throughout Changes to Internal/External Clock, Internal Clock Frequency Updated Outline Dimensions .. 55 Parameter, Table 1 ... 5 Changes to Ordering Guide ... 55 Changes to Figure 7 and Figure 8 ... 14 Changes to Table 6 .. 17
3/2013—Rev. C to Rev. D
Changes to Table 9 .. 18 Changes to CON2 to CON0 Description; Table 22 .. 28 Changes to Table 12, Table 13, and Table 14 ... 19 Changes to Equations in Data Output Coding Section ... 33 Changes to Table 19 .. 24 Changes to Table 22 and Table 23 ... 27
12/2011—Rev. B to Rev. C
Changes to Offset Register and Full-Scale Register Sections .. 29 Moved Revision History Section ... 3 Changes to Reference Section ... 31 Changes to Table 6 .. 13 Changes to Data Output Coding Section .. 32 Changes to Sinc4 50 Hz/60 Hz Rejection Section ... 41
4/2010—Rev. A to Rev. B
Changes to Sinc3 50 Hz/60 Hz Rejection Section ... 43 Added 32-Lead LFCSP .. Universal Changes to 50 Hz/60 Hz Rejection, Sinc4 Filter Section .. 47 Changes to Table 7 .. 17 Changes to Summary of Filter Options Section and Table 35 .. 52 Changes to Communications Register, Table 16 ... 20 Updated Outline Dimensions .. 54
7/2009—Revision 0: Initial Version
Changes to Ordering Guide ... 54 Rev. E | Page 3 of 56 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED FAST SETTLING ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX2 GPOCON REGISTER RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Sigma-Delta (Σ-Δ) ADC and Filter Serial Interface Clock Bridge Power-Down Switch Temperature Sensor Digital Outputs Calibration ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS CHANNEL SEQUENCER DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION ENABLE PARITY CLOCK BRIDGE POWER-DOWN SWITCH TEMPERATURE SENSOR LOGIC OUTPUTS CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) FAST SETTLING MODE (SINC4 FILTER) Output Data Rate and Settling Time, Sinc4 Filter 50 Hz/60 Hz Rejection, Sinc4 Filter FAST SETTLING MODE (SINC3 FILTER) Output Data Rate and Settling Time, Sinc3 Filter 50 Hz/60 Hz Rejection, Sinc3 Filter FAST SETTLING MODE (CHOP ENABLED) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION FLOWMETER OUTLINE DIMENSIONS ORDERING GUIDE