Datasheet AD7192 (Analog Devices) - 9

AD7192 CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I)
3
t4
-00 22
I = INPUT, O = OUTPUT
78 0 Figure 3. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
4 -00 22
I = INPUT, O = OUTPUT
78 0 Figure 4. Write Cycle Timing Diagram Rev. A | Page 8 of 40 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS CIRCUIT AND TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW FILTER, OUTPUT DATA RATE, AND SETTLING TIME Chop Disabled Chop Enabled 50 Hz/60Hz Rejection Zero Latency Channel Sequencer Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING CLOCK BURNOUT CURRENTS REFERENCE REFERENCE DETECT RESET SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS ENABLE PARITY CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE