Datasheet AD9239 (Analog Devices) - 7

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AD9239 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless otherwise noted.
Table 4. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK Clock Rate Full 170 100 210 100 250 100 MSPS Clock Pulse Width High (tEH) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns Clock Pulse Width Low (tEL) Full 2.65 2.9 2.15 2.4 1.8 2.0 ns DATA OUTPUT PARAMETERS Data Output Period or UI Full 1/(16 × fCLK) 1/(16 × fCLK) 1/(16 × fCLK) sec (DOUT + x, DOUT − x) Data Output Duty Cycle 25°C 50 50 50 % Data Valid Time 25°C 0.8 0.8 0.8 UI PLL Lock Time (tLOCK) 25°C 4 4 4 µs Wake-Up Time (Standby) 25°C 250 250 250 ns Wake-Up Time (Power-Down)2 25°C 50 50 50 μs Pipeline Latency Full 40 40 40 CLK cycles Data Rate per Channel (NRZ) 25°C 2.72 3.36 4.0 Gbps Deterministic Jitter 25°C 10 10 10 ps max Random Jitter 25°C 6 6 6 ps rms Channel-to-Channel Bit Skew 25°C 0 0 0 sec Channel-to-Channel Packet Skew3 25°C +1 +1 +1 CLK cycles Output Rise/Fall Time 25°C 50 50 50 ps TERMINATION CHARACTERISTICS Differential Termination Resistance 25°C 100 100 100 Ω APERTURE Aperture Delay (tA) 25°C 1.2 1.2 1.2 ns Aperture Uncertainty (Jitter) 25°C 0.2 0.2 0.2 ps rms OUT-OF-RANGE RECOVERY TIME 25°C 1 1 1 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Receiver dependent. 3 See the Digital Start-Up Sequence section. Rev. E | Page 6 of 40 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation Digital Start-Up Sequence Minimize Skew and Time Misalignment (Optional) Link Initialization (Required) Digital Outputs and Timing Digital Output Scrambler and Error Code Correction Error Correction Code Scramblers Inverter Balance Example Calculating the Parity Bits for the Hamming Code TEMPOUT Pin RBIAS Pin VCMx Pins RESET Pin PDWN Pin SDO Pin SDI/SDIO Pin SCLK Pin CSB Pin PGMx Pins Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide