Datasheet AD7656-1, AD7657-1, AD7658-1 (Analog Devices) - 4

ManufacturerAnalog Devices
Description250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 12-Bit ADC
Pages / Page32 / 4 — AD7656-1/AD7657-1/AD7658-1. Data Sheet. Parameter. Min. Typ. Max. Unit. …
RevisionD
File Format / SizePDF / 726 Kb
Document LanguageEnglish

AD7656-1/AD7657-1/AD7658-1. Data Sheet. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments

AD7656-1/AD7657-1/AD7658-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments

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AD7656-1/AD7657-1/AD7658-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (IIN) ±10 µA Typically 10 nA, VIN = 0 V or VDRIVE Input Capacitance (CIN)2 10 pF LOGIC OUTPUTS Output High Voltage (VOH) VDRIVE − 0.2 V ISOURCE = 200 µA Output Low Voltage (VOL) 0.2 V ISINK = 200 µA Floating-State Leakage Current ±10 µA Floating-State Output Capacitance2 10 pF Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 µs Track-and-Hold Acquisition Time1, 2 550 ns Throughput Rate 250 kSPS Parallel interface mode only POWER REQUIREMENTS VDD −5 +16.5 V For the 4 × VREF range, VDD = 10 V to 16.5 V VSS −5 −16.5 V For the 4 × VREF range, VSS= −10 V to −16.5 V AVCC 4.75 5.25 V DVCC 4.75 5.25 V VDRIVE 2.7 5.25 V I 3 TOTAL Digital inputs = 0 V or VDRIVE Normal Mode—Static 18 mA AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V Normal Mode—Operational 26 mA fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V ISS (Operational) 0.25 mA VSS = −16.5 V, fSAMPLE = 250 kSPS IDD (Operational) 0.25 mA VDD = +16.5 V, fSAMPLE = 250 kSPS Partial Power-Down Mode 7 mA AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V Full Power-Down Mode (STBY Pin) 60 µA SCLK on or off, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V Power Dissipation AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V Normal Mode—Static 94 mW Normal Mode—Operational 140 mW fSAMPLE = 250 kSPS Partial Power-Down Mode 40 mW Full Power-Down Mode (STBY Pin) 315 µW 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC. Rev. D | Page 4 of 32 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications AD7656-1 AD7657-1 AD7658-1 Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Track-and-Hold Amplifiers Analog Input ADC Transfer Function Internal/External Reference Typical Connection Diagram Driving the Analog Inputs Interface Options Parallel Interface (SER/PAR SEL = 0) Software Selection of ADCs Changing the Analog Input Range (H/S SEL = 0) Changing the Analog Input Range (H/S SEL = 1) Serial Interface (SER/PAR SEL = 1) Serial Read Operation Daisy-Chain Mode (DCEN = 1, SER/ SEL = 1) Standby/Partial Power-Down Modes of Operation (SER/PAR SEL = 0 or 1) Application Hints Layout Power Supply Configuration Outline Dimensions Ordering Guide