Datasheet AD7262 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators |
| Pages / Page | 33 / 8 — Data Sheet. AD7262. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. … |
| Revision | C |
| File Format / Size | PDF / 896 Kb |
| Document Language | English |
Data Sheet. AD7262. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. ESD CAUTION
Model Line for this Datasheet
Text Version of Document
Data Sheet AD7262 ABSOLUTE MAXIMUM RATINGS Table 3.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a V stress rating only; functional operation of the product at these DRIVE to DGND −0.3 V to AVCC V or any other conditions above those indicated in the operational DRIVE to AGND −0.3 V to AVCC section of this specification is not implied. Operation beyond AVCC to AGND/DGND −0.3 V to +7 V the maximum operating conditions for extended periods may CA_CBVCC to CA_CB_GND −0.3 V to +7 V affect product reliability. CC_CDVCC to CC_CD_GND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V CA_CB_GND/CC_CD_GND to DGND −0.3 V to +0.3 V
ESD CAUTION
Analog Input Voltage to AGND −0.3 V to AVCC + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V VREFA/VREFB Input to AGND −0.3 V to AVCC + 0.3 V COUTA/COUTB/COUTC/COUTD to GND −0.3 V to VDRIVE + 0.3 V CA±/CB±/CC±/CD± to −0.3 V to CA_CB_GND/CC_CD_GND CA_CBVCC/CC_CDVCC + 0.3 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP θJA Thermal Impedance 30°C/W θJC Thermal Impedance 3°C/W LQFP θJA Thermal Impedance 55°C/W θJC Thermal Impedance 16°C/W Pb-Free Temperature, Soldering Reflow 255°C ESD 2 kV Rev. B | Page 7 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a V stress rating only; functional operation of the product at these DRIVE to DGND −0.3 V to AVCC V or any other conditions above those indicated in the operational DRIVE to AGND −0.3 V to AVCC section of this specification is not implied. Operation beyond AVCC to AGND/DGND −0.3 V to +7 V the maximum operating conditions for extended periods may CA_CBVCC to CA_CB_GND −0.3 V to +7 V affect product reliability. CC_CDVCC to CC_CD_GND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V CA_CB_GND/CC_CD_GND to DGND −0.3 V to +0.3 V
ESD CAUTION
Analog Input Voltage to AGND −0.3 V to AVCC + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V VREFA/VREFB Input to AGND −0.3 V to AVCC + 0.3 V COUTA/COUTB/COUTC/COUTD to GND −0.3 V to VDRIVE + 0.3 V CA±/CB±/CC±/CD± to −0.3 V to CA_CB_GND/CC_CD_GND CA_CBVCC/CC_CDVCC + 0.3 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP θJA Thermal Impedance 30°C/W θJC Thermal Impedance 3°C/W LQFP θJA Thermal Impedance 55°C/W θJC Thermal Impedance 16°C/W Pb-Free Temperature, Soldering Reflow 255°C ESD 2 kV Rev. B | Page 7 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
