Datasheet AD7262 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators |
| Pages / Page | 33 / 9 — AD7262. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 48 47 … |
| Revision | C |
| File Format / Size | PDF / 896 Kb |
| Document Language | English |
AD7262. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 48 47 46 45 44 43 42 41 40 39 38 37. 36 CAL. A_CBVCC. PIN 1
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AD7262 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ND ND _G _G B A B A + – + – _C F ND F CC + – + – _C ND CC A A B B A RE A A B B A RE C C C C C V AG AV G0 G1 G2 G3 C C C C C V AG AV G0 G1 G2 G3 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 C 1 36 CAL A_CBVCC PIN 1 AV 2 INDICATOR 35 CS C 1 36 CAL CC A_CBVCC AV 2 35 CS V 3 34 SCLK CC A– V 3 34 SCLK A– V 4 33 AV A+ CC V 4 33 AV A+ CC AGND 5 32 D AGND 5 32 D OUTA AD7262 OUTA AD7262 AGND 6 31 D AGND 6 31 D TOP VIEW OUTB OUTB TOP VIEW AVCC 7 (Not to Scale) 30 COUTA AVCC 7 (Not to Scale) 30 COUTA AGND 8 29 COUTB AGND 8 29 C V 9 28 DGND OUTB B+ V 10 27 V B– DRIVE V 9 28 DGND B+ AV 11 26 C CC OUTC 10 27 V V DRIVE C 12 25 C B– C_CDVCC OUTD AVCC 11 26 COUTC CC_CDVCC 12 25 COUTD 13 14 15 16 17 18 19 20 21 22 23 24 + – + – B IN 13 14 15 16 17 18 19 20 21 22 23 24 C C D D ND F ND CC D2 D1 C C C C P P D SEL + – + – B _G RE AV C C D D IN AG ND F ND CC D2 D1 D V D0/ EF C C C C P P D SEL P R _G RE AG AV _C D V D0/ EF C P R
003
C _C C C
07606-
NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST
004
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS.
07606- Figure 3. 48-Lead LQFP Pin Configuration Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
2, 7, 11, 20, 33, 41 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the AD7262/AD7262-5. All AVCC pins can be tied together. Decouple this supply to AGND with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor. 1 CA_CBVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and Comparator B. Decouple this supply to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 12 CC_CDVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and Comparator D. Decouple this supply to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 4, 3 VA+, VA− Analog Inputs of ADC A. True differential input pair. 9, 10 VB+, VB− Analog Inputs of ADC B. True differential input pair. 43, 18 VREFA, VREFB Reference Input/Output. Decoupling capacitors connect to these pins to decouple the internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple the reference. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 34 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A minimum of 31 clocks is required to perform the conversion and access the 12-bit result. 36 CAL Logic Input. Initiates an internal offset calibration. 21 PD2 Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1 and PD0 pins (see Table 7). 22 PD1 Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD0 pins (see Table 7). Rev. B | Page 8 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
AD7262 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ND ND _G _G B A B A + – + – _C F ND F CC + – + – _C ND CC A A B B A RE A A B B A RE C C C C C V AG AV G0 G1 G2 G3 C C C C C V AG AV G0 G1 G2 G3 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 C 1 36 CAL A_CBVCC PIN 1 AV 2 INDICATOR 35 CS C 1 36 CAL CC A_CBVCC AV 2 35 CS V 3 34 SCLK CC A– V 3 34 SCLK A– V 4 33 AV A+ CC V 4 33 AV A+ CC AGND 5 32 D AGND 5 32 D OUTA AD7262 OUTA AD7262 AGND 6 31 D AGND 6 31 D TOP VIEW OUTB OUTB TOP VIEW AVCC 7 (Not to Scale) 30 COUTA AVCC 7 (Not to Scale) 30 COUTA AGND 8 29 COUTB AGND 8 29 C V 9 28 DGND OUTB B+ V 10 27 V B– DRIVE V 9 28 DGND B+ AV 11 26 C CC OUTC 10 27 V V DRIVE C 12 25 C B– C_CDVCC OUTD AVCC 11 26 COUTC CC_CDVCC 12 25 COUTD 13 14 15 16 17 18 19 20 21 22 23 24 + – + – B IN 13 14 15 16 17 18 19 20 21 22 23 24 C C D D ND F ND CC D2 D1 C C C C P P D SEL + – + – B _G RE AV C C D D IN AG ND F ND CC D2 D1 D V D0/ EF C C C C P P D SEL P R _G RE AG AV _C D V D0/ EF C P R
003
C _C C C
07606-
NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST
004
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS.
07606- Figure 3. 48-Lead LQFP Pin Configuration Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
2, 7, 11, 20, 33, 41 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the AD7262/AD7262-5. All AVCC pins can be tied together. Decouple this supply to AGND with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor. 1 CA_CBVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and Comparator B. Decouple this supply to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 12 CC_CDVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and Comparator D. Decouple this supply to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 4, 3 VA+, VA− Analog Inputs of ADC A. True differential input pair. 9, 10 VB+, VB− Analog Inputs of ADC B. True differential input pair. 43, 18 VREFA, VREFB Reference Input/Output. Decoupling capacitors connect to these pins to decouple the internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple the reference. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 34 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A minimum of 31 clocks is required to perform the conversion and access the 12-bit result. 36 CAL Logic Input. Initiates an internal offset calibration. 21 PD2 Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1 and PD0 pins (see Table 7). 22 PD1 Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD0 pins (see Table 7). Rev. B | Page 8 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
