Datasheet AD9230-11 (Analog Devices)

11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter AD9230-11 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD SNR = 62.5 dBFS @ fIN up to 70 MHz @ 200 MSPS ENOB of 10.2 @ fIN up to 70 MHz @ 200 MSPS (−1.0 dBFS) REFERENCE AD9230-11 SFDR = −77 dBc @ fIN up to 70 MHz @ 200 MSPS (−1.0 dBFS) Excellent linearity CML DRVDD DRGND DNL = ±0.15 LSB typical VIN+ TRACK-AND-HOLD VIN– INL = ±0.5 LSB typical ADC 12 OUTPUT 11 LVDS at 200 MSPS (ANSI-644 levels) 12-BIT STAGING D10 TO D0 CORE LVDS 700 MHz full power analog bandwidth CLK+ CLOCK OR+ On-chip reference, no external decoupling required CLK– MANAGEMENT OR– Integrated input buffer and track-and-hold amplifier SERIAL PORT Low power dissipation DCO+ DCO– 373 mW @ 200 MSPS (LVDS SDR mode)
01 0 1- 10
328 mW @ 200 MSPS (LVDS DDR mode) RESET SCLK SDIO CSB
07
Programmable input voltage range
Figure 1.
1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9230-11 is an 11-bit monolithic sampling analog-to- 1. High Performance. Maintains 62.5 dBFS SNR digital converter (ADC) optimized for high performance, @ 200 MSPS with a 70 MHz input. low power, and ease of use. The product operates at up to a 2. Low Power. Consumes only 373 mW @ 200 MSPS. 200 MSPS conversion rate and is optimized for outstanding 3. Ease of Use. LVDS output data and output clock signal dynamic performance in wideband carrier and broadband allow interface to current FPGA technology. The on-chip systems. All necessary functions, including a track-and-hold reference and sample-and-hold provide flexibility in (T/H) amplifier and voltage reference, are included on the system design. Use of a single 1.8 V supply simplifies chip to provide a complete signal conversion solution. system power supply design. The ADC requires a 1.8 V analog voltage supply and a 4. Serial Port Control. Standard serial port interface (SPI) differential clock for full performance operation. The digital supports various product functions, such as data formatting, outputs are LVDS (ANSI-644) compatible and support twos disabling the clock duty cycle stabilizer, power-down, gain complement, offset binary format, or Gray code. A data clock adjust, and output test pattern generation. output is available for proper output data timing. 5. Pin-Compatible Family. 10-bit and 12-bit pin-compatible family offered as AD9211 and AD9230. Fabricated on an advanced CMOS process, the AD9230-11 is available in a 56-lead lead frame chip scale package, specified over the industrial temperature range (−40°C to +85°C).
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE