Datasheet AD7764 (Analog Devices) - 5

link to page 19 link to page 19 link to page 6 link to page 6 link to page 6 link to page 6
AD7764 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Decimate 64× Normal Power Mode MCLK = 40 MHz, ODR = 312.5 kHz, fIN = 1 kHz sine wave Dynamic Range Modulator inputs shorted 105 109 dB Differential amplifier inputs shorted 107.3 dB SNR2 102.7 104 dB SFDR Nonharmonic 130 dBFS Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB Input amplitude = −6 dB −103 dB IMD Input amplitude = −6 dB, fIN A = 100.3 kHz, fIN B = 97.3 kHz Second-order terms −118 dB Third-order terms −108 dB Low Power Mode Dynamic Range Modulator inputs shorted 105 106 dB Differential amplifier inputs shorted 105.3 dB SNR2 Input amplitude = −0.5 dB 103 dB 102 dB SFDR Nonharmonic 110 dBFS THD Input amplitude = −0.5 dB −105 dB Input amplitude = −6 dB −111 −100 dB DC ACCURACY Resolution Guaranteed monotonic to 24 bits 24 Bits Integral Nonlinearity Normal power mode 0.0036 % Low power mode 0.0014 % Zero Error Normal power mode 0.006 0.03 % Including on-chip amplifier 0.04 % Low power mode 0.002 0.024 % Gain Error 0.018 % Including on-chip amplifier 0.04 % Zero Error Drift Does not include on-chip amplifier 0.00006 %FS/°C Gain Error Drift Does not include on-chip amplifier 0.00005 %FS/°C DIGITAL FILTER CHARACTERISTICS Normal and low power modes Pass-Band Ripple 0.1 dB Pass Band3 −1 dB frequency ODR × kHz 0.4016 −3 dB Bandwidth3 ODR × kHz 0.4096 Stop Band3 Beginning of stop band ODR × 0.5 kHz Stop-Band Attenuation Decimate 64× and decimate 128× modes −120 dB Decimate 256× −115 dB Group Delay See Table 8 and Table 9 ANALOG INPUT Differential Input Voltage Modulator input pins: VIN+ − VIN−, VREF+ = 4.096 V ±3.2768 V p-p Input Capacitance At on-chip differential amplifier inputs 5 pF At modulator inputs 29 pF REFERENCE INPUT/OUTPUT VREF+ Input Voltage AVDD3 = 5 V ± 5% 4.096 V VREF+ Input DC Leakage Current ±1 µA VREF+ Input Capacitance 5 pF Rev. B | Page 4 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE