Datasheet AD9212 (Analog Devices)

Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC Data Sheet AD9212 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS AD9212 10 SNR = 60.8 dB (to Nyquist) VIN + A SERIAL D + A ADC ENOB = 9.8 bits VIN – A LVDS D – A SFDR = 80 dBc (to Nyquist) 10 VIN + B D + B SERIAL Excellent linearity ADC VIN – B LVDS D – B DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical) 10 VIN + C SERIAL D + C Serial LVDS (ANSI-644, default) ADC VIN – C LVDS D – C Low power, reduced signal option (similar to IEEE 1596.3) 10 Data and frame clock outputs VIN + D SERIAL D + D ADC VIN – D LVDS D – D 325 MHz, full-power analog bandwidth 10 2 V p-p input voltage range VIN + E SERIAL D + E ADC D – E 1.8 V supply operation VIN – E LVDS Serial port control 10 VIN + F D + F SERIAL ADC Full-chip and individual-channel power-down modes VIN – F LVDS D – F Flexible bit orientation 10 VIN + G SERIAL D + G Built-in and custom digital test pattern generation ADC VIN – G LVDS D – G Programmable clock and data alignment 10 Programmable output resolution VIN + H SERIAL D + H ADC VIN – H LVDS D – H Standby mode VREF APPLICATIONS SENSE FCO+ 0.5V FCO– Medical imaging and nondestructive ultrasound DATA RATE REFT REF MULTIPLIER Portable ultrasound and digital beam-forming systems REFB SELECT SERIAL PORT DCO+ INTERFACE DCO– Quadrature radio receivers Diversity radio receivers
01 0
RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK–
8- 96
Tape drives ODM DTP
05 Figure 1.
Optical networking Test equipment
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable
GENERAL DESCRIPTION
clock and data alignment and programmable digital test pattern The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an generation. The available digital test patterns include built-in on-chip sample-and-hold circuit designed for low cost, low power, deterministic and pseudorandom patterns, along with custom user- small size, and ease of use. Operating at a conversion rate of up to defined test patterns entered via the serial port interface (SPI). 65 MSPS, it is optimized for outstanding dynamic performance The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It is and low power in applications where a small package size is critical. specified over the industrial temperature range of −40°C to +85°C. The ADC requires a single 1.8 V power supply and LVPECL-/
PRODUCT HIGHLIGHTS
CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are 1. Small Footprint. Eight ADCs are contained in a small package. required for many applications. 2. Low Power of 100 mW per Channel at 65 MSPS. 3. Ease of Use. A data clock output (DCO) operates up to The ADC automatically multiplies the sample rate clock for 300 MHz and supports double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock (DCO) 4. User Flexibility. SPI control offers a wide range of flexible for capturing data on the output and a frame clock (FCO) for features to meet specific system requirements. signaling a new output byte are provided. Individual channel 5. Pin-Compatible Family. This includes the AD9222 (12-bit) power-down is supported and typically consumes less than and AD9252 (14-bit). 2 mW when all channels are disabled.
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide