Datasheet AD9246 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter |
| Pages / Page | 45 / 8 — AD9246. SWITCHING SPECIFICATIONS. Table 4. AD9246BCPZ-80 AD9246BCPZ-105 … |
| Revision | A |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
AD9246. SWITCHING SPECIFICATIONS. Table 4. AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125. Parameter. Temp
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AD9246 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4. AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125 Parameter 1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Full 20 80 20 105 20 125 MSPS Conversion Rate, DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period Full 12.5 9.5 8 ns CLK Pulse Width High, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns CLK Pulse Width High, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 3.6 4 4.4 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)2 Full 3.1 3.9 4.8 3.1 3.9 4.8 3.1 3.9 4.8 ns DCO Propagation Delay (tDCO) Full 4.4 4.4 4.4 ns Setup Time (tS) Full 4.9 5.7 3.4 4.3 2.6 3.5 ns Hold Time (tH) Full 5.9 6.8 4.4 5.3 3.7 4.5 ns Pipeline Delay (Latency) Full 12 12 12 cycles Aperture Delay (tA) Full 0.8 0.8 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 2 3 Cycles SERIAL PORT INTERFACE4 SCLK Period (tCLK) Full 40 40 40 ns SCLK Pulse Width High Time (tHI) Full 16 16 16 ns SCLK Pulse Width Low Time (tLO) Full 16 16 16 ns SDIO to SCLK Setup Time (tDS) Full 5 5 5 ns SDIO to SCLK Hold Time (tDH) Full 2 2 2 ns CSB to SCLK Setup Time (tS) Full 5 5 5 ns CSB to SCLK Hold Time (tH) Full 2 2 2 ns 1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 57 and the Serial Port Interface (SPI) section.
TIMING DIAGRAM N + 2 N + 1 N + 3 N N + 4 N + 8 tA N + 5 N + 6 N + 7 tCLK CLK+ CLK– tPD DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 tS tH tDCO tCLK
02 0
DCO
1- 49 05 Figure 2. Timing Diagram Rev. A | Page 7 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
AD9246 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4. AD9246BCPZ-80 AD9246BCPZ-105 AD9246BCPZ-125 Parameter 1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Full 20 80 20 105 20 125 MSPS Conversion Rate, DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period Full 12.5 9.5 8 ns CLK Pulse Width High, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns CLK Pulse Width High, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 3.6 4 4.4 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)2 Full 3.1 3.9 4.8 3.1 3.9 4.8 3.1 3.9 4.8 ns DCO Propagation Delay (tDCO) Full 4.4 4.4 4.4 ns Setup Time (tS) Full 4.9 5.7 3.4 4.3 2.6 3.5 ns Hold Time (tH) Full 5.9 6.8 4.4 5.3 3.7 4.5 ns Pipeline Delay (Latency) Full 12 12 12 cycles Aperture Delay (tA) Full 0.8 0.8 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 2 3 Cycles SERIAL PORT INTERFACE4 SCLK Period (tCLK) Full 40 40 40 ns SCLK Pulse Width High Time (tHI) Full 16 16 16 ns SCLK Pulse Width Low Time (tLO) Full 16 16 16 ns SDIO to SCLK Setup Time (tDS) Full 5 5 5 ns SDIO to SCLK Hold Time (tDH) Full 2 2 2 ns CSB to SCLK Setup Time (tS) Full 5 5 5 ns CSB to SCLK Hold Time (tH) Full 2 2 2 ns 1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 57 and the Serial Port Interface (SPI) section.
TIMING DIAGRAM N + 2 N + 1 N + 3 N N + 4 N + 8 tA N + 5 N + 6 N + 7 tCLK CLK+ CLK– tPD DATA N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 tS tH tDCO tCLK
02 0
DCO
1- 49 05 Figure 2. Timing Diagram Rev. A | Page 7 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
