Datasheet AD9219 (Analog Devices)

Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC Data Sheet AD9219 FEATURES FUNCTIONAL BLOCK DIAGRAM 4 ADCs integrated into 1 package AVDD PDWN DRVDD DRGND 94 mW ADC power per channel at 65 MSPS AD9219 SNR = 60 dB (to Nyquist) 10 VIN + A PIPELINE SERIAL D + A ENOB = 9.7 bits VIN – A ADC LVDS D – A SFDR = 78 dBc (to Nyquist) 10 VIN + B Excellent linearity PIPELINE SERIAL D + B VIN – B ADC LVDS D – B DNL = ±0.2 LSB (typical) 10 INL = ±0.3 LSB (typical) VIN + C PIPELINE SERIAL D + C VIN – C ADC LVDS D – C Serial LVDS (ANSI-644, default) 10 Low power, reduced signal option (similar to IEEE 1596.3) VIN + D SERIAL PIPELINE D + D Data and frame clock outputs VIN – D LVDS D – D ADC 315 MHz full-power analog bandwidth VREF SENSE FCO+ 2 V p-p input voltage range +– 0.5V FCO– DATA RATE 1.8 V supply operation REFT REF MULTIPLIER SERIAL PORT Serial port control REFB SELECT DCO+ INTERFACE DCO– Full-chip and individual-channel power-down modes
1 -00
Flexible bit orientation RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
26 57 0
Built-in and custom digital test pattern generation
Figure 1.
Programmable clock and data alignment
The ADC automatically multiplies the sample rate clock for the
Programmable output resolution
appropriate LVDS serial data rate. A data clock output (DCO) for
Standby mode
capturing data on the output and a frame clock output (FCO)
APPLICATIONS
for signaling a new output byte are provided. Individual-channel
Medical imaging and nondestructive ultrasound
power-down is supported and typically consumes less than
Portable ultrasound and digital beam-forming systems
2 mW when all channels are disabled.
Quadrature radio receivers
The ADC contains several features designed to maximize
Diversity radio receivers
flexibility and minimize system cost, such as programmable
Tape drives
clock and data alignment and programmable digital test pattern
Optical networking
generation. The available digital test patterns include built-in
Test equipment
deterministic and pseudorandom patterns, along with custom user-
GENERAL DESCRIPTION
defined test patterns entered via the serial port interface (SPI). The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con- The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is verter (ADC) with an on-chip sample-and-hold circuit designed specified over the industrial temperature range of −40°C to +85°C. for low cost, low power, small size, and ease of use. The product
PRODUCT HIGHLIGHTS
operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications 1. Small Footprint. Four ADCs are contained in a small, space- where a small package size is critical. saving package. 2. Low power of 94 mW/channel at 65 MSPS. The ADC requires a single 1.8 V power supply and LVPECL-/ 3. Ease of Use. A data clock output (DCO) is provided that CMOS-/LVDS-compatible sample rate clock for full performance operates at frequencies of up to 390 MHz and supports operation. No external reference or driver components are double data rate (DDR) operation. required for many applications. 4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit).
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide