Datasheet AD7760 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer |
| Pages / Page | 37 / 8 — TIMING DIAGRAMS. DRDY. RD/WR. D[0:15]. DATA MSW. LSW + STATUS. t15. t16. … |
| Revision | A |
| File Format / Size | PDF / 866 Kb |
| Document Language | English |
TIMING DIAGRAMS. DRDY. RD/WR. D[0:15]. DATA MSW. LSW + STATUS. t15. t16. t17. t18. REGISTER ADDRESS. REGISTER DATA
Model Line for this Datasheet
Text Version of Document
AD7760
TIMING DIAGRAMS DRDY t t 1 5 t6 CS t2 t t 7 3 RD/WR t t 4 8
2 0 -0
D[0:15] DATA MSW LSW + STATUS
5 7 9 4 0 Figure 2. Filtered Output—Parallel Interface Timing Diagram
CS t15 t16 RD/WR t17 t18
4 0 -0
D[0:15] REGISTER ADDRESS REGISTER DATA
5 7 9 4 0 Figure 3. AD7760 Register Write Rev. A | Page 7 of 36
TIMING DIAGRAMS DRDY t t 1 5 t6 CS t2 t t 7 3 RD/WR t t 4 8
2 0 -0
D[0:15] DATA MSW LSW + STATUS
5 7 9 4 0 Figure 2. Filtered Output—Parallel Interface Timing Diagram
CS t15 t16 RD/WR t17 t18
4 0 -0
D[0:15] REGISTER ADDRESS REGISTER DATA
5 7 9 4 0 Figure 3. AD7760 Register Write Rev. A | Page 7 of 36
