Datasheet AD7942 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 14-Bit, 250 kSPS PulSAR , Pseudo Differential ADC in MSOP/LFCSP |
| Pages / Page | 25 / 6 — Data Sheet. AD7942. TIMING SPECIFICATIONS. Table 3. Parameter. Symbol … |
| Revision | C |
| File Format / Size | PDF / 467 Kb |
| Document Language | English |
Data Sheet. AD7942. TIMING SPECIFICATIONS. Table 3. Parameter. Symbol Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
link to page 7 link to page 7 link to page 6
Data Sheet AD7942 TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V1, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 3. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Available Data tCONV 0.5 2.2 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 4 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) tSCK VIO ≥ 4.5 V 17 ns VIO ≥ 3 V 18 ns VIO ≥ 2.7 V 19 ns VIO ≥ 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data-Valid Delay tDSDO VIO ≥ 4.5 V 14 ns VIO ≥ 3 V 15 ns VIO ≥ 2.7 V 16 ns VIO ≥ 2.3 V 17 ns CNV or SDI Low to SDO D13 MSB Valid (CS Mode) tEN VIO ≥ 4.5 V 15 ns VIO ≥ 2.7 V 18 ns VIO ≥ 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO ≥ 4.5 V 15 ns VIO ≥ 2.3 V 26 ns 1 See Figure 2 and Figure 3 for load conditions. Rev. C | Page 5 of 24 Document Outline Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface /CS Mode 3-Wire Without Busy Indicator /CS Mode 3-Wire with Busy Indicator /CS Mode 4-Wire Without Busy Indicator /CS Mode 4-Wire with Busy Indicator Chain Mode Without Busy Indicator Chain Mode with Busy Indicator Application Hints Layout Evaluating the Performance of AD7942 Outline Dimensions Ordering Guide
Data Sheet AD7942 TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V1, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 3. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Available Data tCONV 0.5 2.2 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 4 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) tSCK VIO ≥ 4.5 V 17 ns VIO ≥ 3 V 18 ns VIO ≥ 2.7 V 19 ns VIO ≥ 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data-Valid Delay tDSDO VIO ≥ 4.5 V 14 ns VIO ≥ 3 V 15 ns VIO ≥ 2.7 V 16 ns VIO ≥ 2.3 V 17 ns CNV or SDI Low to SDO D13 MSB Valid (CS Mode) tEN VIO ≥ 4.5 V 15 ns VIO ≥ 2.7 V 18 ns VIO ≥ 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO ≥ 4.5 V 15 ns VIO ≥ 2.3 V 26 ns 1 See Figure 2 and Figure 3 for load conditions. Rev. C | Page 5 of 24 Document Outline Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface /CS Mode 3-Wire Without Busy Indicator /CS Mode 3-Wire with Busy Indicator /CS Mode 4-Wire Without Busy Indicator /CS Mode 4-Wire with Busy Indicator Chain Mode Without Busy Indicator Chain Mode with Busy Indicator Application Hints Layout Evaluating the Performance of AD7942 Outline Dimensions Ordering Guide
