Datasheet AD9444 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 14-Bit, 80 MSPS A/D Converter |
| Pages / Page | 41 / 4 — AD9444. DC SPECIFICATIONS. Table 1. AD9444BSVZ-80. Parameter Temp. Test. … |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
AD9444. DC SPECIFICATIONS. Table 1. AD9444BSVZ-80. Parameter Temp. Test. Level. Min Typ. Max Unit
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AD9444 DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit
RESOLUTION Full VI 14 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error Full VI 6 ±0.3 6 mV Gain Error1 Full VI −3.0 ±0.4 +3.0 % FSR Differential Nonlinearity (DNL)2 Full VI −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL)2 25°C I −1.3 ±0.6 +1.3 LSB Full VI −1.7 +1.7 LSB TEMPERATURE DRIFT Offset Error Full V 12 µV/°C Gain Error Full V 0.002 %FS/°C VOLTAGE REFERENCE Output Voltage1 Full VI 0.87 1.0 1.13 V Load Regulation @ 1.0 mA Full V ±2 mV Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA INPUT REFERRED NOISE 25°C V 1.0 LSB rms ANALOG INPUT Input Span Full V 2 V p-p Input Common-Mode Voltage Full V 3.5 V Input Resistance3 Full V 1 kΩ Input Capacitance3 Full V 2.5 pF POWER SUPPLIES Supply Voltage AVDD1 Full IV 3.14 3.3 3.46 V AVDD2 Full IV 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full IV 3.0 3.6 V DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V Supply Current AVDD1 Full VI 217 240 mA AVDD22 Full VI 71 80 mA IDRVDD2—LVDS Outputs Full VI 55 62 mA IDRVDD2—CMOS Outputs Full V 12 mA PSRR Offset Full V 1 mV/V Gain Full V 0.2 %/V POWER CONSUMPTION DC Input—LVDS Outputs Full VI 1.21 1.4 W DC Input—CMOS Outputs Full V 1.07 W Sine Wave Input2—LVDS Outputs Full VI 1.25 W Sine Wave Input2—CMOS Outputs Full V 1.11 W 1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. 2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure fo 6 r the equivalent analog input structure. Rev. 0 | Page 3 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE
AD9444 DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit
RESOLUTION Full VI 14 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error Full VI 6 ±0.3 6 mV Gain Error1 Full VI −3.0 ±0.4 +3.0 % FSR Differential Nonlinearity (DNL)2 Full VI −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL)2 25°C I −1.3 ±0.6 +1.3 LSB Full VI −1.7 +1.7 LSB TEMPERATURE DRIFT Offset Error Full V 12 µV/°C Gain Error Full V 0.002 %FS/°C VOLTAGE REFERENCE Output Voltage1 Full VI 0.87 1.0 1.13 V Load Regulation @ 1.0 mA Full V ±2 mV Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA INPUT REFERRED NOISE 25°C V 1.0 LSB rms ANALOG INPUT Input Span Full V 2 V p-p Input Common-Mode Voltage Full V 3.5 V Input Resistance3 Full V 1 kΩ Input Capacitance3 Full V 2.5 pF POWER SUPPLIES Supply Voltage AVDD1 Full IV 3.14 3.3 3.46 V AVDD2 Full IV 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full IV 3.0 3.6 V DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V Supply Current AVDD1 Full VI 217 240 mA AVDD22 Full VI 71 80 mA IDRVDD2—LVDS Outputs Full VI 55 62 mA IDRVDD2—CMOS Outputs Full V 12 mA PSRR Offset Full V 1 mV/V Gain Full V 0.2 %/V POWER CONSUMPTION DC Input—LVDS Outputs Full VI 1.21 1.4 W DC Input—CMOS Outputs Full V 1.07 W Sine Wave Input2—LVDS Outputs Full VI 1.25 W Sine Wave Input2—CMOS Outputs Full V 1.11 W 1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. 2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure fo 6 r the equivalent analog input structure. Rev. 0 | Page 3 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS Thermal Resistance ESD CAUTION DEFINITIONS OF SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD LVDS EVALUATION BOARD SCHEMATICS LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) CMOS EVALUATION BOARD SCHEMATICS CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE
