Datasheet AD9216 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| Pages / Page | 41 / 7 — SWITCHING SPECIFICATIONS. Table 4. AD9216BCPZ-65. AD9216BCPZ-80. … |
| Revision | A |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
SWITCHING SPECIFICATIONS. Table 4. AD9216BCPZ-65. AD9216BCPZ-80. AD9216BCPZ-105. Parameter. Temp. Test Level. Min. Typ. Max. Unit
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SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4. AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105 Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 65 80 105 MSPS Minimum Conversion Rate Full IV 10 10 10 MSPS CLK Period Full VI 15.4 12.5 9.5 nS CLK Pulse Width High Full VI 4.6 4.4 3.8 nS CLK Pulse Width Low Full VI 4.6 4.4 3.8 nS OUTPUT PARAMETERS1 Output Propagation Delay2 (tPD) 25°C I 4.5 6.4 4.5 6.4 4.5 6.4 nS Valid Time3 (tV) 25°C I 2.0 2.0 2.0 Output Rise Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS Output Fall Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS Output Enable Time4 Full IV 1 1 1 Cycle Output Disable Time4 Full IV 1 1 1 Cycle Pipeline Delay (Latency) Full IV 6 6 6 Cycle APERTURE Aperture Delay (tA) 25°C V 1.5 1.5 1.5 nS Aperture Uncertainty (tJ) 25°C V 0.5 0.5 0.5 pS rms Wake-Up Time5 25°C V 7 7 7 ms OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycle 1 CLOAD equals 5 pF maximum for all output switching parameters. 2 Output delay is measured from clock 50% transition to data 50% transition. 3 Valid time is approximately equal to the minimum output propagation delay. 4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective channel outputs going into high impedance. 5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB. Rev. A | Page 6 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS LOGIC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS OUTPUT CODING TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Shared Reference Mode DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4. AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105 Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 65 80 105 MSPS Minimum Conversion Rate Full IV 10 10 10 MSPS CLK Period Full VI 15.4 12.5 9.5 nS CLK Pulse Width High Full VI 4.6 4.4 3.8 nS CLK Pulse Width Low Full VI 4.6 4.4 3.8 nS OUTPUT PARAMETERS1 Output Propagation Delay2 (tPD) 25°C I 4.5 6.4 4.5 6.4 4.5 6.4 nS Valid Time3 (tV) 25°C I 2.0 2.0 2.0 Output Rise Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS Output Fall Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS Output Enable Time4 Full IV 1 1 1 Cycle Output Disable Time4 Full IV 1 1 1 Cycle Pipeline Delay (Latency) Full IV 6 6 6 Cycle APERTURE Aperture Delay (tA) 25°C V 1.5 1.5 1.5 nS Aperture Uncertainty (tJ) 25°C V 0.5 0.5 0.5 pS rms Wake-Up Time5 25°C V 7 7 7 ms OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycle 1 CLOAD equals 5 pF maximum for all output switching parameters. 2 Output delay is measured from clock 50% transition to data 50% transition. 3 Valid time is approximately equal to the minimum output propagation delay. 4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective channel outputs going into high impedance. 5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB. Rev. A | Page 6 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS LOGIC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS OUTPUT CODING TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Shared Reference Mode DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
