link to page 7 link to page 7 link to page 7 link to page 7 AD7739Data SheetParameter MinTypMaxUnitTestConditions/Comments WRITE OPERATION t11 0 ns CS falling edge to SCLK falling edge setup t12 30 ns Data valid to SCLK rising edge setup time t13 25 ns Data valid after SCLK rising edge hold time t14 50 ns SCLK high pulse width t15 50 ns SCLK low pulse width t16 0 ns CS rising edge after SCLK rising edge hold time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3. 2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 3 This specification is relevant only if CS goes low while SCLK is low. 4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. TIMING DIAGRAMSCSt4tt68SCLKt7t5tt5A9DOUTMSBLSB03742-0-002 Figure 2. Read Cycle Timing Diagram CSt11tt1614SCLKt15t12t13DINMSBLSB03742-0-003 Figure 3. Write Cycle Timing Diagram ISINK (800 A AT DVDD = 5V100 A AT DVDD = 3V)TO OUTPUT1.6VPIN50pFISOURCE (200 A AT DVDD = 5V100 A AT DVDD = 3V)03742-0-004 Figure 4. Load Circuit for Access Time and Bus Relinquish Time Rev. A | Page 6 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Output Noise and Resolution Specification Chopping Enabled Chopping Disabled Register Descriptions Register Access Communications Register 8 Bits, Write-Only Register, Address 0x00 I/O Port Register 8 Bits, Read/Write Register, Address 0x01, Default Value 0x30 + Digital Input Value × 0x40 Revision Register 8 Bits, Read-Only Register, Address 0x02, Default Value 0x09 + Chip Revision × 0x10 Test Register 24 Bits, Read/Write Register, Address 0x03 ADC Status Register 8 Bits, Read-Only Register, Address 0x04, Default Value 0x00 Checksum Register 16 Bits, Read/Write Register, Address 0x05 ADC Zero-Scale Calibration Register 24 Bits, Read/Write Register, Address 0x06, Default Value 0x80 0000 ADC Full-Scale Calibration Register 24 Bits, Read/Write Register, Address 0x07, Default Value 0x80 0000 Channel Data Registers 16-Bit/24-Bit, Read-Only Registers, Address 0x08 to Address 0x0F, Default Width 16 Bits, Default Value 0x8000 Channel Zero-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 0x10 to Address 0x17, Default Value 0x80 0000 Channel Full-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 0x18 to Address 0x1F, Default Value 0x20 0000 Channel Status Registers 8 Bits, Read-Only Registers, Address 0x20 to Address 0x27, Default Value 0x20 × Channel Number Channel Setup Registers 8 Bits, Read/Write Registers, Address 0x28 to Address 0x2F, Default Value 0x00 Channel Conversion Time Registers 8 Bits, Read/Write Registers, Address 0x30 to Address 0x37, Default Value 0x91 Mode Register 8 Bits, Read/Write Register, Address 0x38 to Address 0x3F, Default Value 0x00 Digital Interface Description Hardware Reset Access the AD7739 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode Circuit Description Analog Inputs Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Extended Voltage Range of the Analog Input Voltage Reference Inputs Reference Detect I/O Port Calibration ADC Zero-Scale Self-Calibration ADC Full-Scale Self-Calibration Per Channel System Calibration Outline Dimensions Ordering Guide