Datasheet AD7466, AD7467, AD7468 (Analog Devices) - 5

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AD7466/AD7467/AD7468 AD7467
VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted. The temperature range for the B version is −40°C to +85°C.
Table 2. Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE Maximum/minimum specifications apply as typical figures when VDD = 1.6 V, fIN = 30 kHz sine wave Signal-to-Noise and Distortion (SINAD) 61 dB min See the Terminology section Total Harmonic Distortion (THD) −72 dB max See the Terminology section Peak Harmonic or Spurious Noise (SFDR) −74 dB max See the Terminology section Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section Second-Order Terms −83 dB typ Third-Order Terms −83 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V 1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V 750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V 450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V DC ACCURACY Maximum specifications apply as typical figures when VDD = 1.6 V Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max See the Terminology section Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits; see the Terminology section Offset Error ±0.2 LSB max See the Terminology section Gain Error ±0.2 LSB max See the Terminology section Total Unadjusted Error (TUE) ±1 LSB max See the Terminology section ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V 2 V min 2.7 V ≤ VDD ≤ 3.6 V Input Low Voltage, VINL 0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V 0.3 × VDD V max 1.8 V ≤V DD < 2.7 V 0.8 V max 2.7 V ≤ VDD ≤ 3.6 V Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 μA typ Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance LOGIC OUTPUTS Output High Voltage, VOH VDD − 0.2 V min ISOURCE = 200 μA, VDD = 1.6 V to 3.6 V Output Low Voltage, VOL 0.2 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 3.52 μs max 12 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 275 kSPS max See the Serial Interface section Rev. C | Page 5 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7466 AD7467 AD7468 TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES DC ACCURACY CURVES POWER REQUIREMENT CURVES TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS NORMAL MODE POWER CONSUMPTION Power Consumption Example 1 Power Consumption Example 2 SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7466/AD7467/AD7468 to TMS320C541 Interface AD7466/AD7467/AD7468 to ADSP-218x Interface AD7466/AD7467/AD7468 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE OF THE AD7466 AND AD7467 OUTLINE DIMENSIONS ORDERING GUIDE