Datasheet AD7734 (Analog Devices) - 7

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AD7734 Data Sheet TIMING SPECIFICATIONS
AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3.
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
Master Clock Range 1 6.144 MHz t1 50 ns SYNC Pulse Width t2 500 ns RESET Pulse Width Read Operation t4 0 ns CS Falling Edge to SCLK Falling Edge Setup Time t 1 5 SCLK Falling Edge to Data Valid Delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t 2 5A CS Falling Edge to Data Valid Delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t6 50 ns SCLK High Pulse Width t7 50 ns SCLK Low Pulse Width t8 0 ns CS Rising Edge after SCLK Rising Edge Hold Time t 3 9 10 80 ns Bus Relinquish Time after SCLK Rising Edge Write Operation t11 0 ns CS Falling Edge to SCLK Falling Edge Setup t12 30 ns Data Valid to SCLK Rising Edge Setup Time t13 25 ns Data Valid after SCLK Rising Edge Hold Time t14 50 ns SCLK High Pulse Width t15 50 ns SCLK Low Pulse Width t16 0 ns CS Rising Edge after SCLK Rising Edge Hold Time 1 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 2 This specification is relevant only if CS goes low while SCLK is low. 3 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the device and as such are independent of external bus loading capacitances. Rev. B | Page 6 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REGISTER DESCRIPTION REGISTER ACCESS COMMUNICATIONS REGISTER I/O PORT REGISTER REVISION REGISTER TEST REGISTER ADC STATUS REGISTER CHECKSUM REGISTER ADC ZERO-SCALE CALIBRATION REGISTER ADC FULL-SCALE REGISTER CHANNEL DATA REGISTERS CHANNEL ZERO-SCALE CALIBRATION REGISTERS CHANNEL FULL-SCALE CALIBRATION REGISTERS CHANNEL STATUS REGISTERS CHANNEL SETUP REGISTERS CHANNEL CONVERSION TIME REGISTERS MODE REGISTER DIGITAL INTERFACE DESCRIPTION HARDWARE RESET ACCESS THE AD7734 REGISTERS SINGLE CONVERSION AND READING DATA DUMP MODE CONTINUOUS CONVERSION MODE CONTINUOUS READ (CONTINUOUS CONVERSION) MODE CIRCUIT DESCRIPTION ANALOG FRONT END ANALOG INPUT’S EXTENDED VOLTAGE RANGE CHOPPING MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING Σ-Δ ADC FREQUENCY RESPONSE VOLTAGE REFERENCE INPUTS REFERENCE DETECT I/O PORT CALIBRATION ADC ZERO-SCALE SELF-CALIBRATION PER CHANNEL SYSTEM CALIBRATION OUTLINE DIMENSIONS ORDERING GUIDE