Datasheet AD7655 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Low Cost, 4-Channel, 16-Bit, 500 kSPS PulSAR ADC |
| Pages / Page | 27 / 4 — Data Sheet. AD7655. SPECIFICATIONS. Table 2. Parameter. Test … |
| Revision | E |
| File Format / Size | PDF / 601 Kb |
| Document Language | English |
Data Sheet. AD7655. SPECIFICATIONS. Table 2. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Text Version of Document
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Data Sheet AD7655 SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; al specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits ANALOG INPUT Voltage Range VINx – VINxN 0 2 VREF V Common-Mode Input Voltage VINxN −0.1 +0.5 V Analog Input CMRR fIN = 100 kHz 55 dB Input Current 500 kSPS throughput 45 µA Input Impedance 1 THROUGHPUT SPEED Complete Cycle (2 Channels) Normal mode 2 µs Throughput Rate Normal mode 0 500 kSPS Complete Cycle (2 Channels) Impulse mode 2.25 2.25 µs Throughput Rate Impulse mode 0 444 kSPS DC ACCURACY Integral Linearity Error 2 −6 +6 LSB3 No Missing Codes 15 Bits Transition Noise 0.8 LSB Full-Scale Error 4 TMIN to TMAX ±0.25 ±0.5 % of FSR Full-Scale Error Drift4 ±2 ppm/°C Unipolar Zero Error4 TMIN to TMAX ±0.25 % of FSR Unipolar Zero Error Drift4 ±0.8 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB AC ACCURACY Signal-to-Noise fIN = 100 kHz 86 dB5 Spurious-Free Dynamic Range fIN = 100 kHz 98 dB Total Harmonic Distortion fIN = 100 kHz −96 dB Signal-to-Noise and Distortion fIN = 100 kHz 86 dB fIN = 100 kHz, −60 dB input 30 dB Channel-to-Channel Isolation fIN = 100 kHz −92 dB −3 dB Input Bandwidth 10 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Delay Matching 30 ps Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns REFERENCE External Reference Voltage Range 2.3 2.5 AVDD/2 V External Reference Current Drain 500 kSPS throughput 180 µA DIGITAL INPUTS Logic Levels VIL −0.3 +0.8 V VIH +2.0 DVDD + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS Data Format 6 Pipeline Delay7 VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = −500 µA OVDD − 0.2 V Rev. E | Page 3 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS INPUT CHANNEL MULTIPLEXER DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Channel A/ Output SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Convert External Clock Data Read (Previous) During Convert MICROPROCESSOR INTERFACING SPI INTERFACE (ADSP-2191M) APPLICATION HINTS LAYOUT EVALUATING THE AD7655 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7655 SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; al specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits ANALOG INPUT Voltage Range VINx – VINxN 0 2 VREF V Common-Mode Input Voltage VINxN −0.1 +0.5 V Analog Input CMRR fIN = 100 kHz 55 dB Input Current 500 kSPS throughput 45 µA Input Impedance 1 THROUGHPUT SPEED Complete Cycle (2 Channels) Normal mode 2 µs Throughput Rate Normal mode 0 500 kSPS Complete Cycle (2 Channels) Impulse mode 2.25 2.25 µs Throughput Rate Impulse mode 0 444 kSPS DC ACCURACY Integral Linearity Error 2 −6 +6 LSB3 No Missing Codes 15 Bits Transition Noise 0.8 LSB Full-Scale Error 4 TMIN to TMAX ±0.25 ±0.5 % of FSR Full-Scale Error Drift4 ±2 ppm/°C Unipolar Zero Error4 TMIN to TMAX ±0.25 % of FSR Unipolar Zero Error Drift4 ±0.8 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB AC ACCURACY Signal-to-Noise fIN = 100 kHz 86 dB5 Spurious-Free Dynamic Range fIN = 100 kHz 98 dB Total Harmonic Distortion fIN = 100 kHz −96 dB Signal-to-Noise and Distortion fIN = 100 kHz 86 dB fIN = 100 kHz, −60 dB input 30 dB Channel-to-Channel Isolation fIN = 100 kHz −92 dB −3 dB Input Bandwidth 10 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Delay Matching 30 ps Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns REFERENCE External Reference Voltage Range 2.3 2.5 AVDD/2 V External Reference Current Drain 500 kSPS throughput 180 µA DIGITAL INPUTS Logic Levels VIL −0.3 +0.8 V VIH +2.0 DVDD + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS Data Format 6 Pipeline Delay7 VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = −500 µA OVDD − 0.2 V Rev. E | Page 3 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS INPUT CHANNEL MULTIPLEXER DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Channel A/ Output SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Convert External Clock Data Read (Previous) During Convert MICROPROCESSOR INTERFACING SPI INTERFACE (ADSP-2191M) APPLICATION HINTS LAYOUT EVALUATING THE AD7655 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
