Datasheet AD7485 (Analog Devices) - 10

AD7485 CIRCUIT DESCRIPTION CAPACITIVE CONVERTER OPERATION DAC
The AD7485 is a 14-bit algorithmic successive-approximation analog-to-digital converter based around a capacitive DAC. It pro- vides the user with track-and-hold, reference, an A/D converter,
A
and versatile interface logic functions on a single chip. The analog
VIN + SW1 CONTROL LOGIC
input signal range that the AD7485 can convert is 0 V to 2.5 V.
B – SW2
The part requires a 2.5 V reference that can be provided from
COMPARATOR
the part’s own internal reference or an external reference source. Figure 3 shows a very simplified schematic of the ADC. The
AGND
Control Logic, SAR, and Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to Figure 5. ADC Acquisition Phase bring the comparator back to a balanced condition.
ADC TRANSFER FUNCTION COMPARATOR
The output coding of the AD7485 is straight binary. The designed code transitions occur midway between successive integer LSB
CAPACITIVE DAC
values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size is VREF/16384. The nominal transfer characteristic for the AD7485 is shown in Figure 6.
VIN SWITCHES VREF 111...111 SAR 111...110 111...000 CONTROL CONTROL 1LSB = V REF/16384 INPUTS LOGIC OUTPUT DATA 011...111 14-BIT SERIAL ADC CODE
Figure 3. Simplified Block Diagram
000...010 000...001
Conversion is initiated on the AD7485 by pulsing the CONVST
000...000 0.5LSB +V
input. On the falling edge of CONVST, the track/hold goes from
0V REF –1.5LSB ANALOG INPUT
track to hold mode and the conversion sequence is started. Conversion time for the part is 24 MCLK periods. Figure 4 shows Figure 6. Transfer Characteristic the ADC during conversion. When conversion starts, SW2 will open and SW1 will move to position B causing the comparator to
POWER SAVING
become unbalanced. The ADC then runs through its successive The AD7485 uses advanced design techniques to achieve very approximation routine and brings the comparator back into a low power dissipation at high throughput rates. In addition to balanced condition. When the comparator is rebalanced, the this, the AD7485 features two power saving modes, NAP mode conversion result is available in the SAR register. and STANDBY mode. These modes are selected by bringing either the NAP or STBY pin to a logic high. When operating the AD7485 with a 25 MHz MCLK in normal,
CAPACITIVE DAC
fully powered mode, the current consumption is 16 mA during conversion and the quiescent current is 12 mA. Operating at a throughput rate of 500 kSPS, the conversion time of 960 ns
A
contributes 38.4 mW to the overall power dissipation.
VIN + SW1 CONTROL LOGIC
( ) ( )
B
ns/ s × V × mA = . mW 960 2 5 16 38 4
– SW2 COMPARATOR
For the remaining 1.04 µs of the cycle, the AD7485 dissipates 31.2 mW of power.
AGND
. /s s V mA . mW ( )×( × ) = Figure 4. ADC Conversion Phase 1 04 2 5 12 31 2 Thus the power dissipated during each cycle is: At the end of conversion, track-and-hold returns to tracking mode and the acquisition time begins. The track/hold acquisition 38 4 . mW + 31 2 . mW = 69 6 . mW time is 70 ns. Figure 5 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN. REV. A –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track/Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Typical Performance Characteristics CIRCUIT DESCRIPTION CONVERTER OPERATION ADC TRANSFER FUNCTION POWER SAVING SERIAL INTERFACE Driving the CONVST Pin Board Layout and Grounding OUTLINE DIMENSIONS