Datasheet AD7476A, AD7477A, AD7478A (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 8-Bit, 1 MSPS, Low-Power A/D Converter in SC70 and MSOP Packages |
| Pages / Page | 28 / 9 — Data Sheet. AD7476A/AD7477A/AD7478A. Timing Diagrams. Timing Example 2. … |
| Revision | G |
| File Format / Size | PDF / 548 Kb |
| Document Language | English |
Data Sheet. AD7476A/AD7477A/AD7478A. Timing Diagrams. Timing Example 2. 200. IOL. TO OUTPUT. 1.6V. PIN. 50pF. Timing Example 1. tCONVERT. SCLK
Model Line for this Datasheet
- AD7476AAKSZ-500RL7 AD7476AAKSZ-REEL7 AD7476ABKSZ-500RL7 AD7476ABKSZ-REEL7 AD7476ABRMZ AD7476ABRMZ-REEL AD7476ABRMZ-REEL7 AD7476AWYRMZ AD7476AWYRMZ-RL7 AD7476AYKSZ-500RL7 AD7476AYKSZ-REEL7 AD7476AYRMZ AD7476AYRMZ-REEL7
Text Version of Document
link to page 9 link to page 9 link to page 9
Data Sheet AD7476A/AD7477A/AD7478A Timing Diagrams Timing Example 2 200
µ
A IOL
Having fSCLK = 5 MHz and a throughput is 315 kSPS yields a cycle time of
TO OUTPUT 1.6V PIN CL
t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs
50pF 200
µ
A I
where:
OH
02930-002 Figure 2. Load Circuit for Digital Output Timing Specifications t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies the requirement of 250 ns for tACQ.
Timing Example 1
From Figure 4, t Having f ACQ is comprised of SCLK = 20 MHz and a throughput of 1 MSPS, a cycle time of 2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns maximum t This allows a value of 128 ns for t 2 + 12.5 (1/fSCLK) + tACQ = 1 µs QUIET, satisfying the minimum requirement of 50 ns. where: In this example and with other, slower clock values, the signal t2 = 10 ns min, leaving tACQ to be 365 ns. This 365 ns satisfies the may already be acquired before the conversion is complete, but requirement of 250 ns for tACQ. it is still necessary to leave 50 ns minimum tQUIET between conversions. In Example 2, acquire the signal fully at From Figure 4, tACQ is comprised of approximately Point C in Figure 4. 2.5 (1/fSCLK) + t8 + tQUIET where: t8 = 36 ns maximum. This allows a value of 204 ns for tQUIET, satisfying the minimum requirement of 50 ns.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t t5 t8 3 t4 t7 tQUIET Z ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0 SDATA THREE- THREE-STATE STATE 4 LEADING ZEROS
02930-003 Figure 3. AD7476A Serial Interface Timing Diagram
CS tCONVERT t2 B C SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET 12.5(1/fSCLK) tACQ 1/THROUGHPUT
02930-004 Figure 4. Serial Interface Timing Example Rev. G | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476A SPECIFICATIONS AD7477A SPECIFICATIONS AD7478A SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION THE CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
Data Sheet AD7476A/AD7477A/AD7478A Timing Diagrams Timing Example 2 200
µ
A IOL
Having fSCLK = 5 MHz and a throughput is 315 kSPS yields a cycle time of
TO OUTPUT 1.6V PIN CL
t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs
50pF 200
µ
A I
where:
OH
02930-002 Figure 2. Load Circuit for Digital Output Timing Specifications t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies the requirement of 250 ns for tACQ.
Timing Example 1
From Figure 4, t Having f ACQ is comprised of SCLK = 20 MHz and a throughput of 1 MSPS, a cycle time of 2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns maximum t This allows a value of 128 ns for t 2 + 12.5 (1/fSCLK) + tACQ = 1 µs QUIET, satisfying the minimum requirement of 50 ns. where: In this example and with other, slower clock values, the signal t2 = 10 ns min, leaving tACQ to be 365 ns. This 365 ns satisfies the may already be acquired before the conversion is complete, but requirement of 250 ns for tACQ. it is still necessary to leave 50 ns minimum tQUIET between conversions. In Example 2, acquire the signal fully at From Figure 4, tACQ is comprised of approximately Point C in Figure 4. 2.5 (1/fSCLK) + t8 + tQUIET where: t8 = 36 ns maximum. This allows a value of 204 ns for tQUIET, satisfying the minimum requirement of 50 ns.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t t5 t8 3 t4 t7 tQUIET Z ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0 SDATA THREE- THREE-STATE STATE 4 LEADING ZEROS
02930-003 Figure 3. AD7476A Serial Interface Timing Diagram
CS tCONVERT t2 B C SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET 12.5(1/fSCLK) tACQ 1/THROUGHPUT
02930-004 Figure 4. Serial Interface Timing Example Rev. G | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476A SPECIFICATIONS AD7477A SPECIFICATIONS AD7478A SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION THE CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
