Datasheet AD73360L (Analog Devices) - 8

AD73360L TERMINOLOGY ABBREVIATIONS Absolute Gain
ADC Analog-to-Digital Converter. Absolute gain is a measure of converter gain for a known signal. BW Bandwidth. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for each ADC. The absolute gain specification CRx A Control Register where x is a placeholder for is used for gain tracking error specification. an alphabetic character (A–E). There are eight read/write control registers on the AD73360L—
Crosstalk
designated CRA through CRE. Crosstalk is due to coupling of signals from a given channel to an adjacent channel. It is defined as the ratio of the amplitude of CRx:n A bit position, where n is a placeholder for a the coupled signal to the amplitude of the input signal. Crosstalk numeric character (0–7), within a control regis- is expressed in dB. ter; where x is a placeholder for an alphabetic character (A–E). Position 7 represents the MSB
Gain Tracking Error
and Position 0 represents the LSB. Gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. The DMCLK Device (Internal) Master Clock. This is the absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz internal master clock resulting from the external for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by master clock (MCLK) being divided by the on- definition. chip master clock divider.
Group Delay
FSLB Frame Sync Loop-Back—where the SDOFS of Group delay is defined as the derivative of radian phase with the final device in a cascade is connected to the respect to radian frequency, dø(f)/df. Group delay is a measure RFS and TFS of the DSP and the SDIFS of first of average delay of a system as a function of frequency. A linear device in the cascade. Data input and output system with a constant group delay has a linear phase response. occur simultaneously. In the case of non-FSLB, The deviation of group delay from a constant indicates the SDOFS and SDO are connected to the Rx Port degree of nonlinear phase response of the system. of the DSP while SDIFS and SDI are connected to the Tx Port.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured PGA Programmable Gain Amplifier. at the output of the device when the input is grounded (mea- SC Switched Capacitor. sured in the frequency range 0 Hz–4 kHz). SNR Signal-to-Noise Ratio.
Intermodulation Distortion
SPORT Serial Port. With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion THD Total Harmonic Distortion. products at sum and difference frequencies of mfa ± nfb where VBW Voice Bandwidth. m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For final testing, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to noise on the power supply. Power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which each ADC updates its output register. It is set relative to the DMCLK and the programmable sample rate setting.
SNR + THD
Signal-to-noise ratio plus harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in a given frequency range, including harmonics but excluding dc. REV. 0 –7–