Datasheet AD73360L (Analog Devices) - 9

AD73360L FUNCTIONAL DESCRIPTION Analog Sigma-Delta Modulator General Description
The AD73360L input channels employ a sigma-delta conver- The AD73360L is a six-input channel, 16-bit, analog front end. sion technique, which provides a high resolution 16-bit output It comprises six independent encoder channels each featuring with system filtering being implemented on-chip. signal conditioning, programmable gain amplifier, sigma-delta Sigma-delta converters employ a technique known as over- A/D converter and decimator sections. Each of these sections is sampling, where the sampling rate is many times the highest described in further detail below. frequency of interest. In the case of the AD73360L, the initial
Encoder Channel
sampling rate of the sigma-delta modulator is DMCLK/8. The Each encoder channel consists of a signal conditioner, a switched main effect of oversampling is that the quantization noise is capacitor PGA, and a sigma-delta analog-to-digital converter spread over a very wide bandwidth, up to fS/2 = DMCLK/16 (ADC). An on-board digital filter, which forms part of the (Figure 6a). This means that the noise in the band of interest is sigma-delta ADC, also performs critical system-level filtering. much reduced. Another complementary feature of sigma-delta Due to the high-level of oversampling, the input antialias require- converters is the use of a technique called noise-shaping. This ments are reduced such that a simple single pole RC stage is technique has the effect of pushing the noise from the band of sufficient to give adequate attenuation in the band of interest. interest to an out-of-band position (Figure 6b). The combina- tion of these techniques, followed by the application of a digital
Signal Conditioner
Each analog channel has an independent signal conditioning filter, reduces the noise in band sufficiently to ensure good block. This allows the analog input to be configured by the user dynamic performance from the part (Figure 6c). depending on whether differential or single-ended mode is used.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modula- tor. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table II, may be used to increase the signal level applied to the ADC from
BAND f OF S/2
low-output sources such as microphones, and can be used to
INTEREST DMCLK/16
a. avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maxi- mum input voltage permitted. The PGA gain is set by bits IGS0, IGS1, and IGS2 in control Registers D, E, and F.
NOISE-SHAPING Table II. PGA Settings for the Encoder Channel BAND fS/2 IxGS2 IxGS1 IxGS0 Gain (dB) OF DMCLK/16 INTEREST
b. 0 0 0 0 0 0 1 6 0 1 0 12 0 1 1 18 1 0 0 20
DIGITAL FILTER
1 0 1 26 1 1 0 32 1 1 1 38
BAND f OF S/2 INTEREST DMCLK/16 ADC
c. Each channel has its own ADC consisting of an analog sigma- delta modulator and a digital antialiasing decimation filter. The Figure 6. Sigma-Delta Noise Reduction sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. –8– REV. 0