Datasheet AD7660 (Analog Devices) - 4

AD7660 Parameter Conditions Min Typ Max Unit
TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 +85 ∞C NOTES 1LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 mV. 2Typical rms noise at worst-case transitions and temperatures. 3See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 5Tested in Parallel Reading Mode. 6With all digital inputs forced to DVDD or DGND respectively. Specifications subject to change without notice.
TIMING SPECIFICATIONS (–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 11 AND 12 Convert Pulsewidth t1 5 ns Time between Conversions t2 10 ms CNVST LOW to BUSY HIGH Delay t3 15 ns BUSY HIGH All Modes Except in t4 2 ms Master Serial Read after Convert Mode Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 2 ms Acquisition Time t8 8 ms RESET Pulsewidth t9 10 ns REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 2 ms DATA Valid to BUSY LOW Delay t11 45 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 5 15 ns REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay t17 500 ns SYNC Asserted to SCLK First Edge Delay t18 4 ns Internal SCLK Period t19 40 75 ns Internal SCLK HIGH (INVSCLK Low)2 t20 30 ns Internal SCLK LOW (INVSCLK Low)2 t21 9.5 ns SDOUT Valid Setup Time t22 4.5 ns SDOUT Valid Hold Time t23 3 ns SCLK Last Edge to SYNC Delay t24 3 CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read after Convert t28 3.2 ms CNVST LOW to SYNC Asserted Delay t29 1.5 ms SYNC Deasserted to BUSY LOW Delay t30 50 ns REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)1 External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 16 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 2If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice. REV. E –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION VS. THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS Bipolar and Wider Input Ranges Layout Evaluating the AD7660 Performance OUTLINE DIMENSIONS Revision History