Datasheet AD73360 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs |
| Pages / Page | 36 / 8 — AD73360. S/(N+D) – dB. 100. –10–85 –75 –65 –55 –45 –35 –25 –15. TO … |
| Revision | B |
| File Format / Size | PDF / 381 Kb |
| Document Language | English |
AD73360. S/(N+D) – dB. 100. –10–85 –75 –65 –55 –45 –35 –25 –15. TO OUTPUT. +2.1V. 3.17. IN –. dBm0. PIN. 15pF. IOH. dB – 40. MCLK. S/(N+D). SCLK*
Model Line for this Datasheet
Text Version of Document
AD73360 80 t1 t2 70 60 50 t3 40
Figure 1. MCLK Timing
30 S/(N+D) – dB 20 10 100
A I 0 OL –10–85 –75 –65 –55 –45 –35 –25 –15 –5 5 TO OUTPUT +2.1V V 3.17 IN – dBm0 PIN CL 15pF
Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz)
100
A IOH
Figure 2. Load Circuit for Timing Specifications
80 70 60 t t2 t 1 3 50 dB – 40 MCLK 30 t S/(N+D) 13 20 SCLK* t5 t6 10 t4 0 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). –10–85 –75 –65 –55 –45 –35 –25 –15 –5 5
Figure 3. SCLK Timing
V 3.17 IN – dBm0
Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz)
SE (I) THREE- STATE SCLK (O) t7 SDIFS (I) t8 t8 t7 SDI (I) D15 D14 D1 D0 D15 t9 t THREE- 10 SDOFS (O) STATE t THREE- t 11 12 STATE SDO (O) D15 D2 D1 D0 D15 D14
Figure 4. Serial Port (SPORT) REV. B –7–
Figure 1. MCLK Timing
30 S/(N+D) – dB 20 10 100
A I 0 OL –10–85 –75 –65 –55 –45 –35 –25 –15 –5 5 TO OUTPUT +2.1V V 3.17 IN – dBm0 PIN CL 15pF
Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz)
100
A IOH
Figure 2. Load Circuit for Timing Specifications
80 70 60 t t2 t 1 3 50 dB – 40 MCLK 30 t S/(N+D) 13 20 SCLK* t5 t6 10 t4 0 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). –10–85 –75 –65 –55 –45 –35 –25 –15 –5 5
Figure 3. SCLK Timing
V 3.17 IN – dBm0
Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz)
SE (I) THREE- STATE SCLK (O) t7 SDIFS (I) t8 t8 t7 SDI (I) D15 D14 D1 D0 D15 t9 t THREE- 10 SDOFS (O) STATE t THREE- t 11 12 STATE SDO (O) D15 D2 D1 D0 D15 D14
Figure 4. Serial Port (SPORT) REV. B –7–
