Datasheet AD7723 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16-Bit, 1.2 MSPS, CMOS Sigma-Delta ADC |
| Pages / Page | 33 / 9 — AD7723. 32 CLKIN CYCLES. CLKIN. FSI. t14. SCO. (CFMT = 0). 16 CLKIN … |
| Revision | C |
| File Format / Size | PDF / 555 Kb |
| Document Language | English |
AD7723. 32 CLKIN CYCLES. CLKIN. FSI. t14. SCO. (CFMT = 0). 16 CLKIN CYCLES. FSO. t13. SDO. D15. D14. D13
Model Line for this Datasheet
Text Version of Document
link to page 9
AD7723 32 CLKIN CYCLES CLKIN t8 FSI t14 SCO (CFMT = 0) t t 11 12 16 CLKIN CYCLES 16 CLKIN CYCLES FSO t13
006
SDO D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15
01186- Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)
Table 3. Serial Interface (MODE1 = 0, MODE2 = 0) Control Inputs Serial Mode Decimation Ratio (SLDR) Digital Filter Mode (SLP) SCO Frequency (SCR) Output Data Rate SLDR SLP SCR
1 32 Low Pass fCLKIN fCLKIN/32 1 1 0 1 32 Band Pass fCLKIN fCLKIN/32 1 0 0 2 32 Low Pass fCLKIN/2 fCLKIN/32 1 1 1 2 32 Band Pass fCLKIN/2 fCLKIN/32 1 0 1 3 16 Low Pass fCLKIN fCLKIN/16 0 1 0
Table 4. Parallel Interface Control Inputs Digital Filter Mode Decimation Ratio Output Data Rate MODE1 MODE2
Band Pass 32 fCLKIN/32 0 1 Low Pass 32 fCLKIN/32 1 0 Low Pass 16 fCLKIN/16 1 1
DOE t t16 15 SDO
01186-007 Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output Rev. C | Page 8 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT DRIVING THE ANALOG INPUTS APPLYING THE REFERENCE CLOCK GENERATION SYSTEM SYNCHRONIZATION DATA INTERFACING PARALLEL INTERFACE SERIAL INTERFACE TWO-CHANNEL MULTIPLEXED OPERATION SERIAL INTERFACE TO DSPs AD7723 TO ADSP-21xx INTERFACE AD7723 TO SHARC INTERFACE AD7723 TO DSP56002 INTERFACE AD7723 TO TMS320C5x INTERFACE GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
AD7723 32 CLKIN CYCLES CLKIN t8 FSI t14 SCO (CFMT = 0) t t 11 12 16 CLKIN CYCLES 16 CLKIN CYCLES FSO t13
006
SDO D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15
01186- Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)
Table 3. Serial Interface (MODE1 = 0, MODE2 = 0) Control Inputs Serial Mode Decimation Ratio (SLDR) Digital Filter Mode (SLP) SCO Frequency (SCR) Output Data Rate SLDR SLP SCR
1 32 Low Pass fCLKIN fCLKIN/32 1 1 0 1 32 Band Pass fCLKIN fCLKIN/32 1 0 0 2 32 Low Pass fCLKIN/2 fCLKIN/32 1 1 1 2 32 Band Pass fCLKIN/2 fCLKIN/32 1 0 1 3 16 Low Pass fCLKIN fCLKIN/16 0 1 0
Table 4. Parallel Interface Control Inputs Digital Filter Mode Decimation Ratio Output Data Rate MODE1 MODE2
Band Pass 32 fCLKIN/32 0 1 Low Pass 32 fCLKIN/32 1 0 Low Pass 16 fCLKIN/16 1 1
DOE t t16 15 SDO
01186-007 Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output Rev. C | Page 8 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT DRIVING THE ANALOG INPUTS APPLYING THE REFERENCE CLOCK GENERATION SYSTEM SYNCHRONIZATION DATA INTERFACING PARALLEL INTERFACE SERIAL INTERFACE TWO-CHANNEL MULTIPLEXED OPERATION SERIAL INTERFACE TO DSPs AD7723 TO ADSP-21xx INTERFACE AD7723 TO SHARC INTERFACE AD7723 TO DSP56002 INTERFACE AD7723 TO TMS320C5x INTERFACE GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
