Datasheet AD7730, AD7730L (Analog Devices) - 3

ManufacturerAnalog Devices
DescriptionCMOS, 24-Bit Low Power Sigma-Delta ADC for Bridge Transducer Applications
Pages / Page53 / 3 — AD7730/AD7730L. Parameter. B Version1. Units. Conditions/Comments
RevisionB
File Format / SizePDF / 323 Kb
Document LanguageEnglish

AD7730/AD7730L. Parameter. B Version1. Units. Conditions/Comments

AD7730/AD7730L Parameter B Version1 Units Conditions/Comments

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AD7730/AD7730L Parameter B Version1 Units Conditions/Comments
LOGIC INPUTS Input Current ±10 μA max All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage 0.8 V max DVDD = +5 V VINL, Input Low Voltage 0.4 V max DVDD = +3 V VINH, Input High Voltage 2.0 V min SCLK Only (Schmitt Triggered Input) VT+ 1.4/3 V min to V max DVDD = +5 V VT+ 1/2.5 V min to V max DVDD = +3 V VT– 0.8/1.4 V min to V max DVDD = +5 V VT– 0.4/1.1 V min to V max DVDD = +3 V VT+ – VT– 0.4/0.8 V min to V max DVDD = +5 V VT+ – VT– 0.4/0.8 V min to V max DVDD = +3 V MCLK IN Only VINL, Input Low Voltage 0.8 V max DVDD = +5 V VINL, Input Low Voltage 0.4 V max DVDD = +3 V VINH, Input High Voltage 3.5 V min DVDD = +5 V VINH, Input High Voltage 2.5 V min DVDD = +3 V LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage ISINK = 800 μA Except for MCLK OUT14; 0.4 V max V 15 DD = +5 V VOL, Output Low Voltage ISINK = 100 μA Except for MCLK OUT14; 0.4 V max V 15 DD = +3 V VOH, Output High Voltage ISOURCE = 200 μA Except for MCLK OUT14; 4.0 V min V 15 DD = +5 V VOH, Output High Voltage ISOURCE = 100 μA Except for MCLK OUT14; V 15 DD – 0.6 V V min VDD = +3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance2 6 pF typ TRANSDUCER BURNOUT AIN1(+) Current –100 nA nom AIN1(–) Current 100 nA nom Initial Tolerance @ 25°C ±10 % typ Drift2 0.1 %/°C typ OFFSET (TARE) DAC Resolution 6 Bit LSB Size 2.3/2.6 mV min/mV max 2.5 mV Nominal with 5 V Reference (REF IN/2000) DAC Drift16 2.5 ppm/°C max DAC Drift vs. Time4, 16 25 ppm/1000 Hours typ Differential Linearity –0.25/+0.75 LSB max Guaranteed Monotonic SYSTEM CALIBRATION Positive Full-Scale Calibration Limit17 1.05 × FS V max FS Is the Nominal Full-Scale Voltage (10 mV, 20 mV, 40 mV or 80 mV) Negative Full-Scale Calibration Limit17 –1.05 × FS V max Offset Calibration Limit18 –1.05 × FS V max Input Span17 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS Power Supply Voltages AVDD – AGND Voltage +4.75 to +5.25 V min to V max DVDD Voltage +2.7 to +5.25 V min to V max With AGND = 0 V Power Supply Currents External MCLK. Digital I/Ps = 0 V or DVDD AVDD Current (Normal Mode) 10.3 mA max All Input Ranges Except 0 mV to +10 mV and ±10 mV AVDD Current (Normal Mode) 22.3 mA max Input Ranges of 0 mV to +10 mV and ± 10 mV Only DVDD Current (Normal Mode) 1.3 mA max DVDD of 2.7 V to 3.3 V DVDD Current (Normal Mode) 2.7 mA max DVDD of 4.75 V to 5.25 V AVDD + DVDD Current (Standby Mode) 25 μA max Typically 10 μA. External MCLK IN = 0 V or DVDD Power Dissipation AVDD = DVDD = +5 V. Digital I/Ps = 0 V or DVDD Normal Mode 65 mW max All Input Ranges Except 0 mV to +10 mV and ±10 mV 125 mW max Input Ranges of 0 mV to +10 mV and ± 10 mV Only Standby Mode 125 μW max Typically 50 μW. External MCLK IN = 0 V or DVDD REV. B –3–